Angel Pons | 16f6aa8 | 2020-04-05 15:47:21 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 2 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 3 | #include <device/pci_def.h> |
Subrata Banik | 00b7533 | 2020-02-20 12:09:45 +0530 | [diff] [blame] | 4 | #include <intelblocks/cse.h> |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 5 | #include <intelblocks/smihandler.h> |
Subrata Banik | 00b7533 | 2020-02-20 12:09:45 +0530 | [diff] [blame] | 6 | #include <soc/soc_chip.h> |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 7 | #include <soc/pci_devs.h> |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 8 | #include <soc/pm.h> |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 9 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 10 | /* |
| 11 | * Specific SOC SMI handler during ramstage finalize phase |
| 12 | * |
| 13 | * BIOS can't make CSME function disable as is due to POSTBOOT_SAI |
| 14 | * restriction in place from TGP chipset. Hence create SMI Handler to |
| 15 | * perform CSME function disabling logic during SMM mode. |
| 16 | */ |
| 17 | void smihandler_soc_at_finalize(void) |
| 18 | { |
| 19 | const struct soc_intel_tigerlake_config *config; |
| 20 | |
| 21 | config = config_of_soc(); |
| 22 | |
| 23 | if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM)) |
Subrata Banik | 7e89984 | 2018-05-17 18:28:26 +0530 | [diff] [blame] | 24 | heci_disable(); |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 25 | } |
| 26 | |
Kane Chen | 7b7b33e | 2021-05-04 09:49:18 +0800 | [diff] [blame] | 27 | int smihandler_soc_disable_busmaster(pci_devfn_t dev) |
| 28 | { |
| 29 | /* Skip disabling PMC bus master to keep IO decode enabled */ |
| 30 | if (dev == PCH_DEV_PMC) |
| 31 | return 0; |
| 32 | return 1; |
| 33 | } |
| 34 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 35 | const smi_handler_t southbridge_smi[SMI_STS_BITS] = { |
| 36 | [SMI_ON_SLP_EN_STS_BIT] = smihandler_southbridge_sleep, |
| 37 | [APM_STS_BIT] = smihandler_southbridge_apmc, |
| 38 | [PM1_STS_BIT] = smihandler_southbridge_pm1, |
| 39 | [GPE0_STS_BIT] = smihandler_southbridge_gpe0, |
| 40 | [GPIO_STS_BIT] = smihandler_southbridge_gpi, |
| 41 | [ESPI_SMI_STS_BIT] = smihandler_southbridge_espi, |
| 42 | [MCSMI_STS_BIT] = smihandler_southbridge_mc, |
Patrick Georgi | a7ec426 | 2020-03-11 16:31:59 +0100 | [diff] [blame] | 43 | #if CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE) |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 44 | [TCO_STS_BIT] = smihandler_southbridge_tco, |
Patrick Georgi | a7ec426 | 2020-03-11 16:31:59 +0100 | [diff] [blame] | 45 | #endif |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 46 | [PERIODIC_STS_BIT] = smihandler_southbridge_periodic, |
| 47 | [MONITOR_STS_BIT] = smihandler_southbridge_monitor, |
| 48 | }; |