Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | #include <assert.h> |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
| 5 | #include <fsp/api.h> |
| 6 | #include <fsp/ppi/mp_service_ppi.h> |
| 7 | #include <fsp/util.h> |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 8 | #include <option.h> |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 9 | #include <intelblocks/lpss.h> |
Lean Sheng Tan | 58ec51c | 2021-06-09 06:51:22 -0700 | [diff] [blame] | 10 | #include <intelblocks/pmclib.h> |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 11 | #include <intelblocks/xdci.h> |
| 12 | #include <intelpch/lockdown.h> |
| 13 | #include <soc/intel/common/vbt.h> |
| 14 | #include <soc/pci_devs.h> |
| 15 | #include <soc/ramstage.h> |
| 16 | #include <soc/soc_chip.h> |
Tan, Lean Sheng | 09133c7 | 2021-05-26 06:40:56 -0700 | [diff] [blame] | 17 | #include <string.h> |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 18 | #include <types.h> |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 19 | |
Lean Sheng Tan | c6c5443 | 2021-05-30 09:08:35 -0700 | [diff] [blame] | 20 | /* SATA DEVSLP idle timeout default values */ |
| 21 | #define DEF_DMVAL 15 |
| 22 | #define DEF_DITOVAL_MS 625 |
| 23 | |
| 24 | /* Native function controls pads termination */ |
| 25 | #define GPIO_TERM_NATIVE 0x1F |
| 26 | |
Lean Sheng Tan | a96be27 | 2021-06-08 21:41:42 -0700 | [diff] [blame] | 27 | /* PM related values */ |
| 28 | /* Imon offset is defined in 1/1000 increments */ |
| 29 | #define IMON_OFFSET 1 |
| 30 | /* Policy Imon slope is defined in 1/100 increments */ |
| 31 | #define IMON_SLOPE 100 |
| 32 | /* Thermal Design Current current limit in 1/8A units */ |
| 33 | #define TDC_CURRENT_LIMIT_MAX 112 |
| 34 | /* AcLoadline in 1/100 mOhms */ |
| 35 | #define AC_LOADLINE_LANE_0_MAX 112 |
| 36 | #define AC_LOADLINE_LANE_1_MAX 3 |
| 37 | /* DcLoadline in 1/100 mOhms */ |
| 38 | #define DC_LOADLINE_LANE_0_MAX 92 |
| 39 | #define DC_LOADLINE_LANE_1_MAX 3 |
| 40 | /* VR Icc Max limit. 0-255A in 1/4 A units */ |
| 41 | #define ICC_LIMIT_MAX 104 |
| 42 | /* Core Ratio Limit: For overclocking part: LFM to Fused */ |
| 43 | #define CORE_RATIO_LIMIT 0x13 |
| 44 | |
Lean Sheng Tan | 9420e28 | 2021-05-27 22:48:33 -0700 | [diff] [blame] | 45 | /* |
| 46 | * Chip config parameter PcieRpL1Substates uses (UPD value + 1) |
| 47 | * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. |
| 48 | * In order to ensure that mainboard setting does not disable L1 substates |
| 49 | * incorrectly, chip config parameter values are offset by 1 with 0 meaning |
| 50 | * use FSP UPD default. get_l1_substate_control() ensures that the right UPD |
| 51 | * value is set in fsp_params. |
| 52 | * 0: Use FSP UPD default |
| 53 | * 1: Disable L1 substates |
| 54 | * 2: Use L1.1 |
| 55 | * 3: Use L1.2 (FSP UPD default) |
| 56 | */ |
| 57 | static int get_l1_substate_control(enum L1_substates_control ctl) |
| 58 | { |
| 59 | if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) |
| 60 | ctl = L1_SS_L1_2; |
| 61 | return ctl - 1; |
| 62 | } |
| 63 | |
Lean Sheng Tan | 8d4e67d | 2021-06-25 11:23:03 -0700 | [diff] [blame] | 64 | static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg, |
| 65 | const struct soc_intel_elkhartlake_config *config) |
| 66 | { |
| 67 | s_cfg->PchFivrExtV1p05RailEnabledStates = config->fivr.v1p05_state; |
| 68 | s_cfg->PchFivrExtV1p05RailSupportedVoltageStates = config->fivr.v1p05_rail; |
| 69 | s_cfg->PchFivrExtVnnRailEnabledStates = config->fivr.vnn_state; |
| 70 | s_cfg->PchFivrExtVnnRailSupportedVoltageStates = config->fivr.vnn_rail; |
| 71 | s_cfg->PchFivrExtVnnRailSxEnabledStates = config->fivr.vnn_sx_state; |
| 72 | s_cfg->PchFivrVccinAuxLowToHighCurModeVolTranTime = config->fivr.vcc_low_high_us; |
| 73 | s_cfg->PchFivrVccinAuxRetToHighCurModeVolTranTime = config->fivr.vcc_ret_high_us; |
| 74 | s_cfg->PchFivrVccinAuxRetToLowCurModeVolTranTime = config->fivr.vcc_ret_low_us; |
| 75 | s_cfg->PchFivrVccinAuxOffToHighCurModeVolTranTime = config->fivr.vcc_off_high_us; |
| 76 | /* Convert mV to number of 2.5 mV increments */ |
| 77 | s_cfg->PchFivrExtVnnRailSxVoltage = (config->fivr.vnn_sx_mv * 10) / 25; |
| 78 | s_cfg->PchFivrExtV1p05RailIccMaximum = config->fivr.v1p05_icc_max_ma; |
| 79 | s_cfg->FivrSpreadSpectrum = config->fivr.spread_spectrum; |
| 80 | } |
| 81 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 82 | static void parse_devicetree(FSP_S_CONFIG *params) |
| 83 | { |
Tan, Lean Sheng | 09133c7 | 2021-05-26 06:40:56 -0700 | [diff] [blame] | 84 | const struct soc_intel_elkhartlake_config *config = config_of_soc(); |
| 85 | |
| 86 | /* LPSS controllers configuration */ |
| 87 | |
| 88 | /* I2C */ |
Lean Sheng Tan | 8bbff1f | 2021-06-15 22:05:42 -0700 | [diff] [blame] | 89 | FSP_ARRAY_LOAD(params->SerialIoI2cMode, config->SerialIoI2cMode); |
| 90 | FSP_ARRAY_LOAD(params->PchSerialIoI2cPadsTermination, |
| 91 | config->SerialIoI2cPadsTermination); |
Tan, Lean Sheng | 09133c7 | 2021-05-26 06:40:56 -0700 | [diff] [blame] | 92 | |
| 93 | params->PchSerialIoI2cSclPinMux[4] = 0x1B44AC09; //GPIO native mode for GPP_H9 |
| 94 | params->PchSerialIoI2cSdaPinMux[4] = 0x1B44CC08; //GPIO native mode for GPP_H8 |
| 95 | |
| 96 | /* GSPI */ |
Lean Sheng Tan | 8bbff1f | 2021-06-15 22:05:42 -0700 | [diff] [blame] | 97 | FSP_ARRAY_LOAD(params->SerialIoSpiMode, config->SerialIoGSpiMode); |
| 98 | FSP_ARRAY_LOAD(params->SerialIoSpiCsEnable, config->SerialIoGSpiCsEnable); |
| 99 | FSP_ARRAY_LOAD(params->SerialIoSpiCsMode, config->SerialIoGSpiCsMode); |
| 100 | FSP_ARRAY_LOAD(params->SerialIoSpiCsState, config->SerialIoGSpiCsState); |
Tan, Lean Sheng | 09133c7 | 2021-05-26 06:40:56 -0700 | [diff] [blame] | 101 | params->SerialIoSpiCsPolarity[2] = 0; |
| 102 | |
| 103 | /* UART */ |
Lean Sheng Tan | 8bbff1f | 2021-06-15 22:05:42 -0700 | [diff] [blame] | 104 | FSP_ARRAY_LOAD(params->SerialIoUartMode, config->SerialIoUartMode); |
| 105 | FSP_ARRAY_LOAD(params->SerialIoUartDmaEnable, config->SerialIoUartDmaEnable); |
Tan, Lean Sheng | 09133c7 | 2021-05-26 06:40:56 -0700 | [diff] [blame] | 106 | |
| 107 | params->SerialIoUartCtsPinMuxPolicy[0] = 0x2B01320F; //GPIO native mode for GPP_T15 |
| 108 | params->SerialIoUartRtsPinMuxPolicy[0] = 0x2B01220E; //GPIO native mode for GPP_T14 |
| 109 | params->SerialIoUartRxPinMuxPolicy[0] = 0x2B01020C; //GPIO native mode for GPP_T12 |
| 110 | params->SerialIoUartTxPinMuxPolicy[0] = 0x2B01120D; //GPIO native mode for GPP_T13 |
| 111 | |
| 112 | /* Provide correct UART number for FSP debug logs */ |
| 113 | params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 114 | } |
| 115 | |
| 116 | /* UPD parameters to be initialized before SiliconInit */ |
| 117 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
| 118 | { |
Lean Sheng Tan | 9420e28 | 2021-05-27 22:48:33 -0700 | [diff] [blame] | 119 | unsigned int i; |
Subrata Banik | 194f0eb | 2021-06-21 19:27:55 +0530 | [diff] [blame] | 120 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 121 | FSP_S_CONFIG *params = &supd->FspsConfig; |
Lean Sheng Tan | e9ee439 | 2021-05-26 08:11:51 -0700 | [diff] [blame] | 122 | struct soc_intel_elkhartlake_config *config = config_of_soc(); |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 123 | |
| 124 | /* Parse device tree and fill in FSP UPDs */ |
| 125 | parse_devicetree(params); |
| 126 | |
Lean Sheng Tan | e9ee439 | 2021-05-26 08:11:51 -0700 | [diff] [blame] | 127 | /* Load VBT before devicetree-specific config. */ |
| 128 | params->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
| 129 | |
| 130 | /* Check if IGD is present and fill Graphics init param accordingly */ |
Subrata Banik | 5b81b88 | 2021-06-09 03:59:11 +0530 | [diff] [blame] | 131 | params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); |
Lean Sheng Tan | e9ee439 | 2021-05-26 08:11:51 -0700 | [diff] [blame] | 132 | |
| 133 | /* Display config */ |
| 134 | params->DdiPortAHpd = config->DdiPortAHpd; |
| 135 | params->DdiPortADdc = config->DdiPortADdc; |
| 136 | params->DdiPortCHpd = config->DdiPortCHpd; |
| 137 | params->DdiPortCDdc = config->DdiPortCDdc; |
| 138 | |
| 139 | /* Use coreboot MP PPI services if Kconfig is enabled */ |
| 140 | if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) |
| 141 | params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); |
| 142 | |
| 143 | /* Chipset Lockdown */ |
| 144 | if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { |
| 145 | params->PchLockDownGlobalSmi = 0; |
| 146 | params->PchLockDownBiosLock = 0; |
| 147 | params->PchLockDownBiosInterface = 0; |
| 148 | params->PchWriteProtectionEnable[0] = 0; |
| 149 | params->PchUnlockGpioPads = 1; |
| 150 | params->RtcMemoryLock = 0; |
Tim Wawrzynczak | 26a77eb | 2021-08-26 09:20:44 -0600 | [diff] [blame] | 151 | params->SkipPamLock = 1; |
Lean Sheng Tan | e9ee439 | 2021-05-26 08:11:51 -0700 | [diff] [blame] | 152 | } else { |
| 153 | params->PchLockDownGlobalSmi = 1; |
| 154 | params->PchLockDownBiosLock = 1; |
| 155 | params->PchLockDownBiosInterface = 1; |
| 156 | params->PchWriteProtectionEnable[0] = 1; |
| 157 | params->PchUnlockGpioPads = 0; |
| 158 | params->RtcMemoryLock = 1; |
Tim Wawrzynczak | 26a77eb | 2021-08-26 09:20:44 -0600 | [diff] [blame] | 159 | params->SkipPamLock = 0; |
Lean Sheng Tan | e9ee439 | 2021-05-26 08:11:51 -0700 | [diff] [blame] | 160 | } |
| 161 | |
| 162 | /* Disable PAVP */ |
| 163 | params->PavpEnable = 0; |
| 164 | |
| 165 | /* Legacy 8254 timer support */ |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 166 | bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); |
| 167 | params->Enable8254ClockGating = !use_8254; |
Lean Sheng Tan | e9ee439 | 2021-05-26 08:11:51 -0700 | [diff] [blame] | 168 | params->Enable8254ClockGatingOnS3 = 1; |
| 169 | |
Michael Niewöhner | 0e90580 | 2021-09-25 00:10:30 +0200 | [diff] [blame] | 170 | /* |
| 171 | * Legacy PM ACPI Timer (and TCO Timer) |
| 172 | * This *must* be 1 in any case to keep FSP from |
| 173 | * 1) enabling PM ACPI Timer emulation in uCode. |
| 174 | * 2) disabling the PM ACPI Timer. |
| 175 | * We handle both by ourself! |
| 176 | */ |
| 177 | params->EnableTcoTimer = 1; |
| 178 | |
Lean Sheng Tan | e9ee439 | 2021-05-26 08:11:51 -0700 | [diff] [blame] | 179 | /* PCH Master Gating Control */ |
| 180 | params->PchPostMasterClockGating = 1; |
| 181 | params->PchPostMasterPowerGating = 1; |
| 182 | |
| 183 | /* HECI */ |
| 184 | params->Heci3Enabled = config->Heci3Enable; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 185 | |
Lean Sheng Tan | 9420e28 | 2021-05-27 22:48:33 -0700 | [diff] [blame] | 186 | /* USB configuration */ |
| 187 | for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
| 188 | params->PortUsb20Enable[i] = config->usb2_ports[i].enable; |
| 189 | params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; |
| 190 | params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; |
| 191 | params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; |
| 192 | params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; |
| 193 | params->Usb2OverCurrentPin[i] = config->usb2_ports[i].enable ? |
| 194 | config->usb2_ports[i].ocpin : 0xff; |
| 195 | } |
| 196 | |
| 197 | for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
| 198 | params->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
| 199 | params->Usb3OverCurrentPin[i] = config->usb3_ports[i].enable ? |
| 200 | config->usb3_ports[i].ocpin : 0xff; |
| 201 | if (config->usb3_ports[i].tx_de_emp) { |
| 202 | params->Usb3HsioTxDeEmphEnable[i] = 1; |
| 203 | params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; |
| 204 | } |
| 205 | if (config->usb3_ports[i].tx_downscale_amp) { |
| 206 | params->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 207 | params->Usb3HsioTxDownscaleAmp[i] = |
| 208 | config->usb3_ports[i].tx_downscale_amp; |
| 209 | } |
| 210 | } |
| 211 | |
| 212 | params->UsbClockGatingEnable = 1; |
| 213 | params->UsbPowerGatingEnable = 1; |
| 214 | |
Angel Pons | c7cfe0b | 2021-06-23 12:39:22 +0200 | [diff] [blame] | 215 | params->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG); |
Lean Sheng Tan | 9420e28 | 2021-05-27 22:48:33 -0700 | [diff] [blame] | 216 | |
| 217 | /* PCIe root ports config */ |
| 218 | for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { |
| 219 | params->PcieRpClkReqDetect[i] = |
| 220 | !config->PcieRpClkReqDetectDisable[i]; |
| 221 | params->PcieRpL1Substates[i] = |
| 222 | get_l1_substate_control(config->PcieRpL1Substates[i]); |
| 223 | params->PcieRpLtrEnable[i] = !config->PcieRpLtrDisable[i]; |
| 224 | params->PcieRpAdvancedErrorReporting[i] = |
| 225 | !config->PcieRpAdvancedErrorReportingDisable[i]; |
| 226 | params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i]; |
| 227 | params->PciePtm[i] = config->PciePtm[i]; |
| 228 | params->PcieRpLtrMaxNoSnoopLatency[i] = 0x1003; |
| 229 | params->PcieRpLtrMaxSnoopLatency[i] = 0x1003; |
| 230 | /* Virtual Channel 1 to Traffic Class mapping */ |
| 231 | params->PcieRpVc1TcMap[i] = 0x60; |
| 232 | } |
| 233 | |
Lean Sheng Tan | c6c5443 | 2021-05-30 09:08:35 -0700 | [diff] [blame] | 234 | /* SATA config */ |
Subrata Banik | 5b81b88 | 2021-06-09 03:59:11 +0530 | [diff] [blame] | 235 | params->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA); |
Lean Sheng Tan | c6c5443 | 2021-05-30 09:08:35 -0700 | [diff] [blame] | 236 | if (params->SataEnable) { |
| 237 | params->SataMode = config->SataMode; |
| 238 | params->SataSalpSupport = config->SataSalpSupport; |
| 239 | params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable); |
| 240 | |
| 241 | for (i = 0; i < CONFIG_MAX_SATA_PORTS; i++) { |
| 242 | params->SataPortsEnable[i] = config->SataPortsEnable[i]; |
| 243 | params->SataPortsDevSlp[i] = config->SataPortsDevSlp[i]; |
| 244 | if (config->SataPortsEnableDitoConfig[i]) { |
| 245 | params->SataPortsDmVal[i] = |
| 246 | config->SataPortsDmVal[i] ? : DEF_DMVAL; |
| 247 | params->SataPortsDitoVal[i] = |
| 248 | config->SataPortsDitoVal[i] ? : DEF_DITOVAL_MS; |
| 249 | } |
| 250 | } |
| 251 | } |
| 252 | |
| 253 | /* SDCard config */ |
Subrata Banik | 5b81b88 | 2021-06-09 03:59:11 +0530 | [diff] [blame] | 254 | params->ScsSdCardEnabled = is_devfn_enabled(PCH_DEVFN_SDCARD); |
Lean Sheng Tan | c6c5443 | 2021-05-30 09:08:35 -0700 | [diff] [blame] | 255 | if (params->ScsSdCardEnabled) { |
| 256 | params->SdCardPowerEnableActiveHigh = config->SdCardPowerEnableActiveHigh; |
| 257 | params->SdCardGpioCmdPadTermination = GPIO_TERM_NATIVE; |
| 258 | params->SdCardGpioDataPadTermination[0] = GPIO_TERM_NATIVE; |
| 259 | params->SdCardGpioDataPadTermination[1] = GPIO_TERM_NATIVE; |
| 260 | params->SdCardGpioDataPadTermination[2] = GPIO_TERM_NATIVE; |
| 261 | params->SdCardGpioDataPadTermination[3] = GPIO_TERM_NATIVE; |
| 262 | } |
| 263 | |
| 264 | /* eMMC config */ |
Subrata Banik | 5b81b88 | 2021-06-09 03:59:11 +0530 | [diff] [blame] | 265 | params->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC); |
Lean Sheng Tan | c6c5443 | 2021-05-30 09:08:35 -0700 | [diff] [blame] | 266 | if (params->ScsEmmcEnabled) { |
| 267 | params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; |
| 268 | params->ScsEmmcDdr50Enabled = config->ScsEmmcDdr50Enabled; |
| 269 | } |
| 270 | |
Lean Sheng Tan | a96be27 | 2021-06-08 21:41:42 -0700 | [diff] [blame] | 271 | /* Thermal config */ |
Subrata Banik | 194f0eb | 2021-06-21 19:27:55 +0530 | [diff] [blame] | 272 | params->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF); |
Lean Sheng Tan | a96be27 | 2021-06-08 21:41:42 -0700 | [diff] [blame] | 273 | params->ProcHotResponse = 0x0; //Disable PROCHOT response |
| 274 | /* Thermal sensor (TS) target width */ |
| 275 | params->DmiTS0TW = 3; |
| 276 | params->DmiTS1TW = 2; |
| 277 | params->DmiTS2TW = 1; |
| 278 | /* Enable memory thermal throttling by default */ |
| 279 | if (!config->MemoryThermalThrottlingDisable) { |
| 280 | params->PchMemoryPmsyncEnable[0] = 1; |
| 281 | params->PchMemoryPmsyncEnable[1] = 1; |
| 282 | params->PchMemoryC0TransmitEnable[0] = 1; |
| 283 | params->PchMemoryC0TransmitEnable[1] = 1; |
| 284 | } |
| 285 | |
| 286 | /* TccActivationOffset config */ |
| 287 | params->TccActivationOffset = config->tcc_offset; |
| 288 | params->TccOffsetClamp = config->tcc_offset_clamp; |
| 289 | params->TccOffsetLock = 0x1; //lock Tcc Offset register |
| 290 | |
| 291 | /* Power management config */ |
| 292 | params->ImonSlope[0] = IMON_SLOPE; |
| 293 | params->ImonOffset[0] = IMON_OFFSET; |
| 294 | params->TdcCurrentLimit[0] = TDC_CURRENT_LIMIT_MAX; |
| 295 | params->AcLoadline[0] = AC_LOADLINE_LANE_0_MAX; |
| 296 | params->DcLoadline[0] = DC_LOADLINE_LANE_0_MAX; |
| 297 | params->AcLoadline[1] = AC_LOADLINE_LANE_1_MAX; |
| 298 | params->DcLoadline[1] = DC_LOADLINE_LANE_1_MAX; |
| 299 | params->IccMax[0] = ICC_LIMIT_MAX; |
| 300 | params->OneCoreRatioLimit = CORE_RATIO_LIMIT; |
| 301 | params->TwoCoreRatioLimit = CORE_RATIO_LIMIT; |
| 302 | params->ThreeCoreRatioLimit = CORE_RATIO_LIMIT; |
| 303 | params->FourCoreRatioLimit = CORE_RATIO_LIMIT; |
| 304 | params->FiveCoreRatioLimit = CORE_RATIO_LIMIT; |
| 305 | params->SixCoreRatioLimit = CORE_RATIO_LIMIT; |
| 306 | params->SevenCoreRatioLimit = CORE_RATIO_LIMIT; |
| 307 | params->EightCoreRatioLimit = CORE_RATIO_LIMIT; |
| 308 | params->PsysPmax = 0; //Set max platform power to auto profile |
| 309 | params->Custom1TurboActivationRatio = 0; |
| 310 | params->Custom2TurboActivationRatio = 0; |
| 311 | params->Custom3TurboActivationRatio = 0; |
| 312 | params->PchPwrOptEnable = 0x1; //Enable PCH DMI Power Optimizer |
| 313 | params->TStates = 0x0; //Disable T state |
| 314 | params->PkgCStateLimit = 0x7; //Set C state limit to C9 |
| 315 | params->FastPkgCRampDisable[0] = 0x1; |
| 316 | params->SlowSlewRate[0] = 0x1; |
| 317 | params->MaxRatio = 0x8; //Set max P state ratio |
| 318 | params->PchEspiLgmrEnable = 0; |
| 319 | params->PchPmPwrBtnOverridePeriod = config->PchPmPwrBtnOverridePeriod; |
| 320 | params->PchS0ixAutoDemotion = 0; |
| 321 | params->PmcV1p05PhyExtFetControlEn = 0x1; |
| 322 | params->PmcV1p05IsExtFetControlEn = 0x1; |
| 323 | /* FIVR config */ |
Lean Sheng Tan | 8d4e67d | 2021-06-25 11:23:03 -0700 | [diff] [blame] | 324 | if (config->fivr.fivr_config_en) { |
| 325 | fill_fsps_fivr_params(params, config); |
| 326 | } |
Lean Sheng Tan | a96be27 | 2021-06-08 21:41:42 -0700 | [diff] [blame] | 327 | |
Lean Sheng Tan | 0cdcdc7 | 2021-06-08 23:41:15 -0700 | [diff] [blame] | 328 | /* FuSa (Functional Safety) config */ |
| 329 | if (!config->FuSaEnable) { |
| 330 | params->DisplayFusaConfigEnable = 0; |
| 331 | params->GraphicFusaConfigEnable = 0; |
| 332 | params->OpioFusaConfigEnable = 0; |
| 333 | params->PsfFusaConfigEnable = 0; |
| 334 | } |
| 335 | |
Lean Sheng Tan | 58ec51c | 2021-06-09 06:51:22 -0700 | [diff] [blame] | 336 | /* PCH GBE config */ |
| 337 | /* |
| 338 | * Due to EHL GBE comes with time sensitive networking (TSN) |
| 339 | * capability integrated, EHL FSP is using PchTsnEnable instead of |
| 340 | * usual PchLanEnable flag for GBE control. Hence, force |
| 341 | * PchLanEnable to disable to avoid it being used in the future. |
| 342 | */ |
| 343 | params->PchLanEnable = 0x0; |
| 344 | params->PchTsnEnable = is_devfn_enabled(PCH_DEVFN_GBE); |
| 345 | if (params->PchTsnEnable) { |
| 346 | params->PchTsnGbeSgmiiEnable = config->PchTsnGbeSgmiiEnable; |
| 347 | params->PchTsnGbeMultiVcEnable = config->PchTsnGbeMultiVcEnable; |
| 348 | /* |
| 349 | * Currently EHL TSN GBE only supports link speed with 2 type of |
| 350 | * PCH XTAL frequency: 24 MHz and 38.4 MHz. |
| 351 | * These are the configs setup for PchTsnGbeLinkSpeed FSP-S UPD: |
| 352 | * 0: 24MHz 2.5Gbps, 1: 24MHz 1Gbps, 2: 38.4MHz 2.5Gbps, |
| 353 | * 3: 38.4MHz 1Gbps |
| 354 | */ |
| 355 | switch (pmc_get_xtal_freq()) { |
| 356 | case XTAL_24_MHZ: |
| 357 | params->PchTsnGbeLinkSpeed = (!!config->PchTsnGbeLinkSpeed); |
| 358 | break; |
| 359 | case XTAL_38_4_MHZ: |
| 360 | params->PchTsnGbeLinkSpeed = (!!config->PchTsnGbeLinkSpeed) + 0x2; |
| 361 | break; |
| 362 | case XTAL_19_2_MHZ: |
| 363 | default: |
| 364 | printk(BIOS_ERR, "XTAL not supported. Disabling PCH TSN GBE.\n"); |
| 365 | params->PchTsnEnable = 0; |
| 366 | devfn_disable(pci_root_bus(), PCH_DEVFN_GBE); |
| 367 | } |
| 368 | } |
| 369 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 370 | /* Override/Fill FSP Silicon Param for mainboard */ |
| 371 | mainboard_silicon_init_params(params); |
| 372 | } |
| 373 | |
| 374 | /* Mainboard GPIO Configuration */ |
| 375 | __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) |
| 376 | { |
| 377 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 378 | } |