Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #ifndef _SOC_CHIP_H_ |
| 4 | #define _SOC_CHIP_H_ |
| 5 | |
| 6 | #include <drivers/i2c/designware/dw_i2c.h> |
| 7 | #include <intelblocks/cfg.h> |
| 8 | #include <intelblocks/gpio.h> |
| 9 | #include <intelblocks/gspi.h> |
Eric Lai | de2ab41 | 2021-01-11 16:14:14 +0800 | [diff] [blame] | 10 | #include <intelblocks/pcie_rp.h> |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 11 | #include <intelblocks/power_limit.h> |
| 12 | #include <soc/gpe.h> |
| 13 | #include <soc/gpio.h> |
| 14 | #include <soc/gpio_defs.h> |
| 15 | #include <soc/pch.h> |
| 16 | #include <soc/pci_devs.h> |
| 17 | #include <soc/pmc.h> |
| 18 | #include <soc/serialio.h> |
| 19 | #include <soc/usb.h> |
| 20 | #include <stdint.h> |
| 21 | |
Tan, Lean Sheng | 33f8fc6 | 2021-05-24 23:15:43 -0700 | [diff] [blame] | 22 | #define MAX_HD_AUDIO_SDI_LINKS 2 |
| 23 | #define MAX_HD_AUDIO_DMIC_LINKS 2 |
| 24 | #define MAX_HD_AUDIO_SNDW_LINKS 4 |
| 25 | #define MAX_HD_AUDIO_SSP_LINKS 6 |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 26 | |
Werner Zeh | bab5d50 | 2021-06-16 12:30:36 +0200 | [diff] [blame] | 27 | /* Define config parameters for In-Band ECC (IBECC). */ |
| 28 | #define MAX_IBECC_REGIONS 8 |
| 29 | |
| 30 | enum ibecc_mode { |
| 31 | IBECC_PER_REGION, |
| 32 | IBECC_NONE, |
| 33 | IBECC_ALL |
| 34 | }; |
| 35 | |
| 36 | struct ehl_ibecc_config { |
| 37 | bool enable; |
| 38 | bool parity_en; |
| 39 | enum ibecc_mode mode; |
| 40 | bool region_enable[MAX_IBECC_REGIONS]; |
| 41 | uint16_t region_base[MAX_IBECC_REGIONS]; |
| 42 | uint16_t region_mask[MAX_IBECC_REGIONS]; |
| 43 | }; |
| 44 | |
Lean Sheng Tan | 58ec51c | 2021-06-09 06:51:22 -0700 | [diff] [blame] | 45 | /* TSN GBE Link Speed: 0: 2.5Gbps, 1: 1Gbps */ |
| 46 | enum tsn_gbe_link_speed { |
| 47 | Tsn_2_5_Gbps, |
| 48 | Tsn_1_Gbps, |
| 49 | }; |
| 50 | |
Lean Sheng Tan | 8d4e67d | 2021-06-25 11:23:03 -0700 | [diff] [blame] | 51 | /* |
| 52 | * Enable external V1P05 Rail in: BIT0:S0i1/S0i2, |
| 53 | * BIT1:S0i3, BIT2:S3, BIT3:S4, BIT4:S5 |
| 54 | * However, EHL does not support S0i1 and S0i2, |
| 55 | * hence removed the option. |
| 56 | */ |
| 57 | enum fivr_states { |
| 58 | FIVR_ENABLE_S0i3 = BIT(1), |
| 59 | FIVR_ENABLE_S3 = BIT(2), |
| 60 | FIVR_ENABLE_S4 = BIT(3), |
| 61 | FIVR_ENABLE_S5 = BIT(4), |
| 62 | FIVR_ENABLE_S3_S4_S5 = FIVR_ENABLE_S3 | FIVR_ENABLE_S4 | FIVR_ENABLE_S5, |
| 63 | FIVR_ENABLE_ALL_SX = FIVR_ENABLE_S0i3 | FIVR_ENABLE_S3_S4_S5, |
| 64 | }; |
| 65 | |
| 66 | /* |
| 67 | * Enable the following for external V1p05 rail |
| 68 | * BIT1: Normal active voltage supported |
| 69 | * BIT2: Minimum active voltage supported |
| 70 | * BIT3: Minimum retention voltage supported |
| 71 | */ |
| 72 | enum fivr_supported_voltage { |
| 73 | FIVR_VOLTAGE_NORMAL = BIT(1), |
| 74 | FIVR_VOLTAGE_MIN_ACTIVE = BIT(2), |
| 75 | FIVR_VOLTAGE_MIN_RETENTION = BIT(3), |
| 76 | FIVR_ENABLE_ALL_VOLTAGE = FIVR_VOLTAGE_NORMAL | FIVR_VOLTAGE_MIN_ACTIVE | |
| 77 | FIVR_VOLTAGE_MIN_RETENTION, |
| 78 | }; |
| 79 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 80 | struct soc_intel_elkhartlake_config { |
| 81 | |
| 82 | /* Common struct containing soc config data required by common code */ |
| 83 | struct soc_intel_common_config common_soc_config; |
| 84 | |
| 85 | /* Common struct containing power limits configuration information */ |
| 86 | struct soc_power_limits_config power_limits_config; |
| 87 | |
| 88 | /* Gpio group routed to each dword of the GPE0 block. Values are |
| 89 | * of the form PMC_GPP_[A:U] or GPD. */ |
| 90 | uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ |
| 91 | uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */ |
| 92 | uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */ |
| 93 | |
| 94 | /* Generic IO decode ranges */ |
| 95 | uint32_t gen1_dec; |
| 96 | uint32_t gen2_dec; |
| 97 | uint32_t gen3_dec; |
| 98 | uint32_t gen4_dec; |
| 99 | |
| 100 | /* Enable S0iX support */ |
| 101 | int s0ix_enable; |
| 102 | /* Enable DPTF support */ |
| 103 | int dptf_enable; |
| 104 | |
| 105 | /* Deep SX enable for both AC and DC */ |
| 106 | int deep_s3_enable_ac; |
| 107 | int deep_s3_enable_dc; |
| 108 | int deep_s5_enable_ac; |
| 109 | int deep_s5_enable_dc; |
| 110 | |
| 111 | /* Deep Sx Configuration |
| 112 | * DSX_EN_WAKE_PIN - Enable WAKE# pin |
| 113 | * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin |
| 114 | * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */ |
| 115 | uint32_t deep_sx_config; |
| 116 | |
| 117 | /* TCC activation offset */ |
| 118 | uint32_t tcc_offset; |
Lean Sheng Tan | a96be27 | 2021-06-08 21:41:42 -0700 | [diff] [blame] | 119 | uint32_t tcc_offset_clamp; |
| 120 | |
| 121 | /* Memory Thermal Throttling: Enable - Default (0) / Disable (1) */ |
| 122 | bool MemoryThermalThrottlingDisable; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 123 | |
Werner Zeh | bab5d50 | 2021-06-16 12:30:36 +0200 | [diff] [blame] | 124 | /* In-Band ECC (IBECC) configuration */ |
| 125 | struct ehl_ibecc_config ibecc; |
| 126 | |
Lean Sheng Tan | 0cdcdc7 | 2021-06-08 23:41:15 -0700 | [diff] [blame] | 127 | /* FuSa (Functional Safety): Disable - Default (0) / Enable (1) */ |
| 128 | bool FuSaEnable; |
| 129 | |
Tan, Lean Sheng | 33f8fc6 | 2021-05-24 23:15:43 -0700 | [diff] [blame] | 130 | /* System Agent dynamic frequency support. |
| 131 | * When enabled memory will be trained at different frequencies. |
| 132 | * 0:Disabled, 1:FixedPoint0(low), 2:FixedPoint1(mid), 3:FixedPoint2 |
| 133 | * (high), 4:Enabled */ |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 134 | enum { |
| 135 | SaGv_Disabled, |
| 136 | SaGv_FixedPoint0, |
| 137 | SaGv_FixedPoint1, |
| 138 | SaGv_FixedPoint2, |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 139 | SaGv_Enabled, |
| 140 | } SaGv; |
| 141 | |
| 142 | /* Rank Margin Tool. 1:Enable, 0:Disable */ |
| 143 | uint8_t RMT; |
| 144 | |
| 145 | /* USB related */ |
Lean Sheng Tan | 9420e28 | 2021-05-27 22:48:33 -0700 | [diff] [blame] | 146 | struct usb2_port_config usb2_ports[10]; |
| 147 | struct usb3_port_config usb3_ports[4]; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 148 | /* Wake Enable Bitmap for USB2 ports */ |
| 149 | uint16_t usb2_wake_enable_bitmap; |
| 150 | /* Wake Enable Bitmap for USB3 ports */ |
| 151 | uint16_t usb3_wake_enable_bitmap; |
| 152 | |
| 153 | /* SATA related */ |
| 154 | uint8_t SataMode; |
| 155 | uint8_t SataSalpSupport; |
Lean Sheng Tan | c6c5443 | 2021-05-30 09:08:35 -0700 | [diff] [blame] | 156 | uint8_t SataPortsEnable[CONFIG_MAX_SATA_PORTS]; |
| 157 | uint8_t SataPortsDevSlp[CONFIG_MAX_SATA_PORTS]; |
| 158 | /* |
| 159 | * Enable(0)/Disable(1) SATA Power Optimizer on PCH side. |
| 160 | * Default 0. Setting this to 1 disables the SATA Power Optimizer. |
| 161 | */ |
| 162 | uint8_t SataPwrOptimizeDisable; |
| 163 | /* |
| 164 | * SATA Port Enable Dito Config. |
| 165 | * Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). |
| 166 | */ |
| 167 | uint8_t SataPortsEnableDitoConfig[CONFIG_MAX_SATA_PORTS]; |
| 168 | /* SataPortsDmVal is the DITO multiplier. Default is 15. */ |
| 169 | uint8_t SataPortsDmVal[CONFIG_MAX_SATA_PORTS]; |
| 170 | /* SataPortsDitoVal is the DEVSLP Idle Timeout, default is 625ms */ |
| 171 | uint16_t SataPortsDitoVal[CONFIG_MAX_SATA_PORTS]; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 172 | |
| 173 | /* Audio related */ |
| 174 | uint8_t PchHdaDspEnable; |
| 175 | uint8_t PchHdaAudioLinkHdaEnable; |
Tan, Lean Sheng | 33f8fc6 | 2021-05-24 23:15:43 -0700 | [diff] [blame] | 176 | uint8_t PchHdaSdiEnable[MAX_HD_AUDIO_SDI_LINKS]; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 177 | uint8_t PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS]; |
| 178 | uint8_t PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS]; |
| 179 | uint8_t PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS]; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 180 | |
| 181 | /* PCIe Root Ports */ |
| 182 | uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; |
Lean Sheng Tan | 9420e28 | 2021-05-27 22:48:33 -0700 | [diff] [blame] | 183 | uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; |
| 184 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 185 | /* PCIe output clocks type to PCIe devices. |
| 186 | * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, |
| 187 | * 0xFF: not used */ |
Rizwan Qureshi | a979460 | 2021-04-08 20:31:47 +0530 | [diff] [blame] | 188 | uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC]; |
Lean Sheng Tan | 9420e28 | 2021-05-27 22:48:33 -0700 | [diff] [blame] | 189 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 190 | /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to |
| 191 | * clksrc. */ |
Rizwan Qureshi | a979460 | 2021-04-08 20:31:47 +0530 | [diff] [blame] | 192 | uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_SRC]; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 193 | |
Lean Sheng Tan | 58ec51c | 2021-06-09 06:51:22 -0700 | [diff] [blame] | 194 | /* Enable PCIe Precision Time Measurement for Root Ports (disabled by default) */ |
Lean Sheng Tan | 9420e28 | 2021-05-27 22:48:33 -0700 | [diff] [blame] | 195 | uint8_t PciePtm[CONFIG_MAX_ROOT_PORTS]; |
| 196 | |
| 197 | /* Probe CLKREQ# signal before enabling CLKREQ# based power management. |
| 198 | * Enable - Default (0) / Disable (1) */ |
| 199 | uint8_t PcieRpClkReqDetectDisable[CONFIG_MAX_ROOT_PORTS]; |
| 200 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 201 | /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ |
Lean Sheng Tan | 9420e28 | 2021-05-27 22:48:33 -0700 | [diff] [blame] | 202 | uint8_t PcieRpAdvancedErrorReportingDisable[CONFIG_MAX_ROOT_PORTS]; |
| 203 | |
| 204 | /* PCIe LTR: Enable - Default (0) / Disable (1) */ |
| 205 | uint8_t PcieRpLtrDisable[CONFIG_MAX_ROOT_PORTS]; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 206 | |
| 207 | /* PCIe RP L1 substate */ |
Eric Lai | de2ab41 | 2021-01-11 16:14:14 +0800 | [diff] [blame] | 208 | enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 209 | |
| 210 | /* SMBus */ |
| 211 | uint8_t SmbusEnable; |
| 212 | |
| 213 | /* eMMC and SD */ |
| 214 | uint8_t ScsEmmcHs400Enabled; |
Lean Sheng Tan | c6c5443 | 2021-05-30 09:08:35 -0700 | [diff] [blame] | 215 | uint8_t ScsEmmcDdr50Enabled; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 216 | |
| 217 | /* Enable if SD Card Power Enable Signal is Active High */ |
| 218 | uint8_t SdCardPowerEnableActiveHigh; |
| 219 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 220 | /* Gfx related */ |
Tan, Lean Sheng | 33f8fc6 | 2021-05-24 23:15:43 -0700 | [diff] [blame] | 221 | uint8_t Heci2Enable; |
| 222 | uint8_t Heci3Enable; |
| 223 | |
| 224 | /* Gfx related */ |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 225 | uint8_t SkipExtGfxScan; |
| 226 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 227 | uint8_t Device4Enable; |
| 228 | |
| 229 | /* HeciEnabled decides the state of Heci1 at end of boot |
| 230 | * Setting to 0 (default) disables Heci1 and hides the device from OS */ |
| 231 | uint8_t HeciEnabled; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 232 | |
| 233 | /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ |
| 234 | uint8_t eist_enable; |
| 235 | |
| 236 | /* Enable C6 DRAM */ |
| 237 | uint8_t enable_c6dram; |
Michael Niewöhner | 0e25580 | 2021-09-15 12:58:11 +0200 | [diff] [blame] | 238 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 239 | /* |
| 240 | * SerialIO device mode selection: |
| 241 | * PchSerialIoDisabled, |
| 242 | * PchSerialIoPci, |
| 243 | * PchSerialIoHidden, |
| 244 | * PchSerialIoLegacyUart, |
| 245 | * PchSerialIoSkipInit |
| 246 | */ |
| 247 | uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; |
| 248 | uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 249 | uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX]; |
| 250 | /* |
Tan, Lean Sheng | 09133c7 | 2021-05-26 06:40:56 -0700 | [diff] [blame] | 251 | * UARTn Default DMA/PIO Mode Enable(1)/Disable(0): |
| 252 | */ |
| 253 | uint8_t SerialIoUartDmaEnable[CONFIG_SOC_INTEL_UART_DEV_MAX]; |
| 254 | /* |
| 255 | * GSPIn Default Chip Enable(1)/Disable(0): |
| 256 | */ |
| 257 | uint8_t SerialIoGSpiCsEnable[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 258 | /* |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 259 | * GSPIn Default Chip Select Mode: |
| 260 | * 0:Hardware Mode, |
| 261 | * 1:Software Mode |
| 262 | */ |
| 263 | uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
| 264 | /* |
| 265 | * GSPIn Default Chip Select State: |
| 266 | * 0: Low, |
| 267 | * 1: High |
| 268 | */ |
| 269 | uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; |
Lean Sheng Tan | 8d4e67d | 2021-06-25 11:23:03 -0700 | [diff] [blame] | 270 | /* |
Tan, Lean Sheng | 09133c7 | 2021-05-26 06:40:56 -0700 | [diff] [blame] | 271 | * SerialIo I2C Pads Termination Config: |
| 272 | * 0x0:Hardware default, |
| 273 | * 0x1:None, |
| 274 | * 0x13:1kOhm weak pull-up, |
| 275 | * 0x15:5kOhm weak pull-up, |
| 276 | * 0x19:20kOhm weak pull-up |
| 277 | */ |
| 278 | uint8_t SerialIoI2cPadsTermination[CONFIG_SOC_INTEL_I2C_DEV_MAX]; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 279 | |
| 280 | /* |
| 281 | * TraceHubMode config |
| 282 | * 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode |
| 283 | */ |
| 284 | uint8_t TraceHubMode; |
| 285 | |
| 286 | /* Debug interface selection */ |
| 287 | enum { |
| 288 | DEBUG_INTERFACE_RAM = (1 << 0), |
| 289 | DEBUG_INTERFACE_UART_8250IO = (1 << 1), |
| 290 | DEBUG_INTERFACE_USB3 = (1 << 3), |
| 291 | DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4), |
| 292 | DEBUG_INTERFACE_TRACEHUB = (1 << 5), |
| 293 | } debug_interface_flag; |
| 294 | |
| 295 | /* GPIO SD card detect pin */ |
| 296 | unsigned int sdcard_cd_gpio; |
| 297 | |
| 298 | /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ |
Angel Pons | 98521c5 | 2021-03-01 21:16:49 +0100 | [diff] [blame] | 299 | bool CnviBtAudioOffload; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 300 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 301 | /* |
| 302 | * Override GPIO PM configuration: |
| 303 | * 0: Use FSP default GPIO PM program, |
| 304 | * 1: coreboot to override GPIO PM program |
| 305 | */ |
| 306 | uint8_t gpio_override_pm; |
| 307 | |
| 308 | /* |
| 309 | * GPIO PM configuration: 0 to disable, 1 to enable power gating |
| 310 | * Bit 6-7: Reserved |
| 311 | * Bit 5: MISCCFG_GPSIDEDPCGEN |
| 312 | * Bit 4: MISCCFG_GPRCOMPCDLCGEN |
| 313 | * Bit 3: MISCCFG_GPRTCDLCGEN |
| 314 | * Bit 2: MISCCFG_GSXLCGEN |
| 315 | * Bit 1: MISCCFG_GPDPCGEN |
| 316 | * Bit 0: MISCCFG_GPDLCGEN |
| 317 | */ |
| 318 | uint8_t gpio_pm[TOTAL_GPIO_COMM]; |
| 319 | |
| 320 | /* DP config */ |
| 321 | /* |
| 322 | * Port config |
| 323 | * 0:Disabled, 1:eDP, 2:MIPI DSI |
| 324 | */ |
| 325 | uint8_t DdiPortAConfig; |
| 326 | uint8_t DdiPortBConfig; |
| 327 | |
| 328 | /* Enable(1)/Disable(0) HPD */ |
| 329 | uint8_t DdiPortAHpd; |
| 330 | uint8_t DdiPortBHpd; |
| 331 | uint8_t DdiPortCHpd; |
| 332 | uint8_t DdiPort1Hpd; |
| 333 | uint8_t DdiPort2Hpd; |
| 334 | uint8_t DdiPort3Hpd; |
| 335 | uint8_t DdiPort4Hpd; |
| 336 | |
| 337 | /* Enable(1)/Disable(0) DDC */ |
| 338 | uint8_t DdiPortADdc; |
| 339 | uint8_t DdiPortBDdc; |
| 340 | uint8_t DdiPortCDdc; |
| 341 | uint8_t DdiPort1Ddc; |
| 342 | uint8_t DdiPort2Ddc; |
| 343 | uint8_t DdiPort3Ddc; |
| 344 | uint8_t DdiPort4Ddc; |
| 345 | |
| 346 | /* Hybrid storage mode enable (1) / disable (0) |
| 347 | * This mode makes FSP detect Optane and NVME and set PCIe lane mode |
| 348 | * accordingly */ |
| 349 | uint8_t HybridStorageMode; |
| 350 | |
| 351 | /* |
| 352 | * Override CPU flex ratio value: |
| 353 | * CPU ratio value controls the maximum processor non-turbo ratio. |
| 354 | * Valid Range 0 to 63. |
| 355 | * In general descriptor provides option to set default cpu flex ratio. |
| 356 | * Default cpu flex ratio 0 ensures booting with non-turbo max frequency. |
| 357 | * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0. |
| 358 | * Only override CPU flex ratio to not boot with non-turbo max. |
| 359 | */ |
| 360 | uint8_t cpu_ratio_override; |
| 361 | |
| 362 | /* Skip CPU replacement check |
| 363 | * 0: disable |
| 364 | * 1: enable |
| 365 | * Setting this option to skip CPU replacement check to avoid the forced MRC training |
| 366 | * for the platforms with soldered down SOC. |
| 367 | */ |
| 368 | uint8_t SkipCpuReplacementCheck; |
| 369 | |
Lean Sheng Tan | 8d4e67d | 2021-06-25 11:23:03 -0700 | [diff] [blame] | 370 | struct { |
| 371 | bool fivr_config_en; |
| 372 | enum fivr_states v1p05_state; |
| 373 | enum fivr_states vnn_state; |
| 374 | enum fivr_states vnn_sx_state; |
| 375 | enum fivr_supported_voltage v1p05_rail; |
| 376 | enum fivr_supported_voltage vnn_rail; |
| 377 | /* Icc max for V1p05 rail in mA */ |
| 378 | unsigned int v1p05_icc_max_ma; |
| 379 | /* Vnn voltage in mV */ |
| 380 | unsigned int vnn_sx_mv; |
| 381 | /* Transition time in microseconds: */ |
| 382 | /* From low current mode voltage to high current mode voltage */ |
| 383 | unsigned int vcc_low_high_us; |
| 384 | /* From retention mode voltage to high current mode voltage */ |
| 385 | unsigned int vcc_ret_high_us; |
| 386 | /* From retention mode voltage to low current mode voltage */ |
| 387 | unsigned int vcc_ret_low_us; |
| 388 | /* From off(0V) to high current mode voltage */ |
| 389 | unsigned int vcc_off_high_us; |
| 390 | /* RFI spread spectrum, in 0.1% increment. Range: 0.0% to 10.0% (0-100). */ |
| 391 | unsigned int spread_spectrum; |
| 392 | } fivr; |
| 393 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 394 | /* |
| 395 | * SLP_S3 Minimum Assertion Width Policy |
| 396 | * 1 = 60us |
| 397 | * 2 = 1ms |
| 398 | * 3 = 50ms (default) |
| 399 | * 4 = 2s |
| 400 | */ |
| 401 | uint8_t PchPmSlpS3MinAssert; |
| 402 | |
| 403 | /* |
| 404 | * SLP_S4 Minimum Assertion Width Policy |
| 405 | * 1 = 1s (default) |
| 406 | * 2 = 2s |
| 407 | * 3 = 3s |
| 408 | * 4 = 4s |
| 409 | */ |
| 410 | uint8_t PchPmSlpS4MinAssert; |
| 411 | |
| 412 | /* |
| 413 | * SLP_SUS Minimum Assertion Width Policy |
| 414 | * 1 = 0ms |
| 415 | * 2 = 500ms |
| 416 | * 3 = 1s |
| 417 | * 4 = 4s (default) |
| 418 | */ |
| 419 | uint8_t PchPmSlpSusMinAssert; |
| 420 | |
| 421 | /* |
| 422 | * SLP_A Minimum Assertion Width Policy |
| 423 | * 1 = 0ms |
| 424 | * 2 = 4s |
| 425 | * 3 = 98ms |
| 426 | * 4 = 2s (default) |
| 427 | */ |
| 428 | uint8_t PchPmSlpAMinAssert; |
| 429 | |
| 430 | /* |
| 431 | * PCH PM Reset Power Cycle Duration |
| 432 | * 0 = 4s (default) |
| 433 | * 1 = 1s |
| 434 | * 2 = 2s |
| 435 | * 3 = 3s |
| 436 | * 4 = 4s |
| 437 | * |
| 438 | * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the |
| 439 | * stretch duration programmed in the following registers: |
| 440 | * - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) |
| 441 | * - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) |
| 442 | * - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) |
| 443 | * - PM_CFG.SLP_LAN_MIN_ASST_WDTH |
| 444 | */ |
| 445 | uint8_t PchPmPwrCycDur; |
Lean Sheng Tan | a96be27 | 2021-06-08 21:41:42 -0700 | [diff] [blame] | 446 | |
| 447 | /* |
| 448 | * PCH power button override period. |
| 449 | * Values: 0x0 - 4s, 0x1 - 6s, 0x2 - 8s, 0x3 - 10s, 0x4 - 12s, 0x5 - 14s |
| 450 | */ |
| 451 | u8 PchPmPwrBtnOverridePeriod; |
Lean Sheng Tan | 58ec51c | 2021-06-09 06:51:22 -0700 | [diff] [blame] | 452 | |
| 453 | /* GBE related */ |
| 454 | /* PCH TSN GBE Link Speed: 0: 2.5Gbps, 1: 1Gbps */ |
| 455 | enum tsn_gbe_link_speed PchTsnGbeLinkSpeed; |
| 456 | /* PCH TSN GBE SGMII Support: Disable (0) / Enable (1) */ |
| 457 | bool PchTsnGbeSgmiiEnable; |
| 458 | /* PCH TSN GBE Multiple Virtual Channel: Disable (0) / Enable (1) */ |
| 459 | bool PchTsnGbeMultiVcEnable; |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 460 | }; |
| 461 | |
| 462 | typedef struct soc_intel_elkhartlake_config config_t; |
| 463 | |
| 464 | #endif |