Angel Pons | 0612b27 | 2020-04-05 15:46:56 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 2 | |
| 3 | #ifndef SOC_INTEL_COMMON_BLOCK_SA_DEF_H |
| 4 | #define SOC_INTEL_COMMON_BLOCK_SA_DEF_H |
| 5 | |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 6 | /* Device 0:0.0 PCI configuration space */ |
| 7 | |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 8 | /* GMCH Graphics Control Register */ |
Subrata Banik | bd6ac22 | 2017-08-21 16:42:15 +0530 | [diff] [blame] | 9 | #define GGC 0x50 |
| 10 | #define G_GMS_OFFSET 0x8 |
| 11 | #define G_GMS_MASK 0xff00 |
| 12 | #define G_GGMS_OFFSET 0x6 |
| 13 | #define G_GGMS_MASK 0xc0 |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 14 | /* DPR register in case CONFIG_SA_ENABLE_DPR is selected by SoC */ |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 15 | #define DPR 0x5c |
| 16 | #define DPR_EPM (1 << 2) |
| 17 | #define DPR_PRS (1 << 1) |
| 18 | #define DPR_SIZE_MASK 0xff0 |
Patrick Rudolph | bf72dcb | 2020-05-12 16:04:47 +0200 | [diff] [blame] | 19 | /* CAPID0_A */ |
| 20 | #define CAPID_ECCDIS (1 << 25) |
| 21 | #define CAPID_DDPCD (1 << 14) |
| 22 | #define CAPID_PDCD (1 << 12) |
| 23 | #define CAPID_DDRSZ(x) (((x) >> 19) & 0x3) |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 24 | |
| 25 | #define PCIEXBAR_LENGTH_64MB 2 |
| 26 | #define PCIEXBAR_LENGTH_128MB 1 |
| 27 | #define PCIEXBAR_LENGTH_256MB 0 |
| 28 | #define PCIEXBAR_PCIEXBAREN (1 << 0) |
| 29 | |
| 30 | #define PAM0 0x80 |
| 31 | #define PAM1 0x81 |
| 32 | #define PAM2 0x82 |
| 33 | #define PAM3 0x83 |
| 34 | #define PAM4 0x84 |
| 35 | #define PAM5 0x85 |
| 36 | #define PAM6 0x86 |
| 37 | |
Tim Wawrzynczak | d87af79 | 2021-08-24 09:20:14 -0600 | [diff] [blame] | 38 | /* PAM0 contains the lock bit */ |
| 39 | #define PAM_LOCK (1 << 0) |
| 40 | |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 41 | /* Device 0:0.0 MMIO space */ |
| 42 | #define MCH_PAIR 0x5418 |
| 43 | |
| 44 | /* |
Martin Roth | f48acbd | 2020-07-24 12:24:27 -0600 | [diff] [blame] | 45 | * IMR register in case CONFIG(SA_ENABLE_IMR) is selected by SoC. |
Subrata Banik | 7609c65 | 2017-05-19 14:50:09 +0530 | [diff] [blame] | 46 | * |
| 47 | * IMR registers are found under MCHBAR. |
| 48 | */ |
| 49 | #define MCH_IMR0_BASE 0x6870 |
| 50 | #define MCH_IMR0_MASK 0x6874 |
| 51 | #define MCH_IMR_PITCH 0x20 |
| 52 | #define MCH_NUM_IMRS 20 |
| 53 | |
| 54 | /* |
| 55 | * System Memory Map Registers |
| 56 | * - top_of_ram -> TSEG - DPR: uncacheable |
| 57 | * - TESG - DPR -> BGSM: cacheable with standard MTRRs and reserved |
| 58 | * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved |
| 59 | * - 4GiB -> TOUUD: cacheable |
| 60 | */ |
| 61 | enum { |
| 62 | SA_TOUUD_REG, |
| 63 | SA_TOLUD_REG, |
| 64 | SA_BGSM_REG, |
| 65 | SA_TSEG_REG, |
| 66 | /* Must be last. */ |
| 67 | MAX_MAP_ENTRIES |
| 68 | }; |
| 69 | |
| 70 | /* |
| 71 | * Set Fixed MMIO range |
| 72 | * REG = Either PCI configuration space registers. |
| 73 | * IS_64_BIT = If registers/offset is 64 bit. |
| 74 | * DESCRIPTION = Name of the register/offset. |
| 75 | */ |
| 76 | struct sa_mem_map_descriptor { |
| 77 | unsigned int reg; |
| 78 | bool is_64_bit; |
| 79 | const char *description; |
| 80 | }; |
| 81 | |
| 82 | #endif /* SOC_INTEL_COMMON_BLOCK_SA_DEF_H */ |