Angel Pons | 0612b27 | 2020-04-05 15:46:56 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Michael Niewöhner | e0ad1fa | 2019-10-28 18:55:14 +0100 | [diff] [blame] | 2 | |
| 3 | #include <arch/romstage.h> |
| 4 | #include <cbmem.h> |
| 5 | #include <console/console.h> |
| 6 | #include <cpu/x86/mtrr.h> |
| 7 | #include <cpu/x86/smm.h> |
Srinidhi N Kaushik | 4eb489f | 2020-11-25 02:21:57 -0800 | [diff] [blame] | 8 | #include <intelblocks/fast_spi.h> |
Michael Niewöhner | e0ad1fa | 2019-10-28 18:55:14 +0100 | [diff] [blame] | 9 | #include <intelblocks/systemagent.h> |
Francois Toguo | 522e0db | 2021-01-21 09:55:19 -0800 | [diff] [blame] | 10 | #include <arch/bert_storage.h> |
Angel Pons | 3dea2b6 | 2020-10-01 22:50:12 +0200 | [diff] [blame] | 11 | #include <types.h> |
Michael Niewöhner | e0ad1fa | 2019-10-28 18:55:14 +0100 | [diff] [blame] | 12 | |
Michael Niewöhner | e75a64f | 2019-10-19 15:17:06 +0200 | [diff] [blame] | 13 | /* |
| 14 | * Expected Host Memory Map (we don't know 100% and not all regions are present on all SoCs): |
| 15 | * |
| 16 | * +---------------------------+ TOUUD |
| 17 | * | | |
| 18 | * +---------------------------+ TOM (if mem > 4GB) |
| 19 | * | CSME UMA (if mem > 4 GiB) | |
| 20 | * +---------------------------+ TOUUD |
| 21 | * | | |
| 22 | * +---------------------------+ 4GiB |
| 23 | * | PCI Address Space | |
| 24 | * +---------------------------+ TOM (if mem < 4GB) |
| 25 | * | CSME UMA (if mem < 4 GiB) | |
| 26 | * +---------------------------+ TOLUD (also maps into MC address space) |
| 27 | * | iGD / DSM | |
| 28 | * +---------------------------+ BDSM |
| 29 | * | GTT / GSM | |
| 30 | * +---------------------------+ TOLM |
| 31 | * | TSEG | |
| 32 | * +---------------------------+ TSEGMB |
| 33 | * | DMA Protected Region | |
| 34 | * +---------------------------+ DPR |
| 35 | * | PRM (C6DRAM/SGX) | |
| 36 | * +---------------------------+ PRMRR |
| 37 | * | Probeless Trace | |
| 38 | * +---------------------------+ ME Stolen |
| 39 | * | PTT | |
| 40 | * +---------------------------+ TOLUM / top_of_ram / cbmem_top |
| 41 | * | CBMEM Root | |
| 42 | * +---------------------------+ |
| 43 | * | FSP Reserved Memory | |
| 44 | * +---------------------------+ |
| 45 | * | various CBMEM entries | |
| 46 | * +---------------------------+ top_of_stack (8 byte aligned) |
| 47 | * | stack (CBMEM entry) | |
| 48 | * +---------------------------+ FSP TOLUM |
| 49 | * | | |
| 50 | * +---------------------------+ 0 |
| 51 | */ |
| 52 | |
Francois Toguo | 522e0db | 2021-01-21 09:55:19 -0800 | [diff] [blame] | 53 | #define BERT_REGION_MAX_SIZE 0x10000 |
| 54 | |
Michael Niewöhner | e0ad1fa | 2019-10-28 18:55:14 +0100 | [diff] [blame] | 55 | void smm_region(uintptr_t *start, size_t *size) |
| 56 | { |
| 57 | *start = sa_get_tseg_base(); |
| 58 | *size = sa_get_tseg_size(); |
| 59 | } |
| 60 | |
Francois Toguo | 522e0db | 2021-01-21 09:55:19 -0800 | [diff] [blame] | 61 | void bert_reserved_region(void **start, size_t *size) |
| 62 | { |
| 63 | *start = cbmem_add(CBMEM_ID_ACPI_BERT, BERT_REGION_MAX_SIZE); |
| 64 | *size = BERT_REGION_MAX_SIZE; |
| 65 | |
Benjamin Doron | 07dda33 | 2021-02-05 00:23:46 +0000 | [diff] [blame] | 66 | printk(BIOS_DEBUG, "Reserving BERT start %lx, size %zx\n", (uintptr_t)*start, *size); |
Francois Toguo | 522e0db | 2021-01-21 09:55:19 -0800 | [diff] [blame] | 67 | } |
| 68 | |
Michael Niewöhner | e0ad1fa | 2019-10-28 18:55:14 +0100 | [diff] [blame] | 69 | void fill_postcar_frame(struct postcar_frame *pcf) |
| 70 | { |
Angel Pons | 3dea2b6 | 2020-10-01 22:50:12 +0200 | [diff] [blame] | 71 | /* FSP does not seem to bother w.r.t. alignment when asked to place cbmem_top() */ |
| 72 | uintptr_t top_of_ram = ALIGN_UP((uintptr_t)cbmem_top(), 8 * MiB); |
Michael Niewöhner | e0ad1fa | 2019-10-28 18:55:14 +0100 | [diff] [blame] | 73 | |
| 74 | /* |
| 75 | * We need to make sure ramstage will be run cached. At this |
| 76 | * point exact location of ramstage in cbmem is not known. |
Angel Pons | 3dea2b6 | 2020-10-01 22:50:12 +0200 | [diff] [blame] | 77 | * Instruct postcar to cache 16 megs below cbmem top which is |
Michael Niewöhner | e0ad1fa | 2019-10-28 18:55:14 +0100 | [diff] [blame] | 78 | * a safe bet to cover ramstage. |
| 79 | */ |
Michael Niewöhner | e0ad1fa | 2019-10-28 18:55:14 +0100 | [diff] [blame] | 80 | printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); |
Angel Pons | 3dea2b6 | 2020-10-01 22:50:12 +0200 | [diff] [blame] | 81 | |
| 82 | postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); |
Michael Niewöhner | e0ad1fa | 2019-10-28 18:55:14 +0100 | [diff] [blame] | 83 | |
| 84 | /* Cache the TSEG region */ |
| 85 | postcar_enable_tseg_cache(pcf); |
Srinidhi N Kaushik | 4eb489f | 2020-11-25 02:21:57 -0800 | [diff] [blame] | 86 | |
| 87 | /* Cache the extended BIOS region if it is supported */ |
| 88 | fast_spi_cache_ext_bios_postcar(pcf); |
Michael Niewöhner | e0ad1fa | 2019-10-28 18:55:14 +0100 | [diff] [blame] | 89 | } |