Gitiles
Code Review Sign In
review.coreboot.org / coreboot / 4e9bb3308e811000eb089be6b03658e4cb9a4717 / . / src / soc / intel / baytrail / refcode_native.c
blob: a9976fb409d350c9cac9e97f6ceb7f227b162af1 [file] [log] [blame]
Mate Kukrie2319492020-07-04 11:20:07 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <device/mmio.h>
4#include <console/console.h>
5#include <cpu/x86/tsc.h>
6#include <device/pci.h>
7#include <delay.h>
8#include <soc/pci_devs.h>
9#include <soc/lpc.h>
10#include <soc/iosf.h>
11#include <soc/iomap.h>
12#include <soc/ramstage.h>
13#include <soc/modphy_table.h>
14
15#define IOSF_READ(op_read, port) \
16 (IOSF_OPCODE(op_read) | IOSF_PORT(port))
17#define IOSF_WRITE(op_write, port) \
18 (IOSF_OPCODE(op_write) | IOSF_PORT(port))
19
20static void program_modphy_table(struct modphy_entry *table)
21{
22 u32 tmp;
23
24 for (; table->port; ++table) {
25 tmp = iosf_read_port(IOSF_READ(table->op_read, table->port), table->reg);
26 iosf_write_port(IOSF_WRITE(table->op_write, table->port), table->reg,
27 (tmp & table->mask) | table->value);
28 }
29}
30
31static void gpio_sc_sdcard_workaround(void)
32{
33 setbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 0));
34 setbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 2));
35 clrbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 1));
36 clrbits32((char *) IO_BASE_ADDRESS + 0x690, (1 << 3));
37 udelay(100);
38 clrbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 0));
39 udelay(100);
40 write32((char *) IO_BASE_ADDRESS + 0x830, 0x78480);
41 udelay(40);
42 write32((char *) IO_BASE_ADDRESS + 0x830, 0x78080);
43 setbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 0));
44 udelay(100);
45 setbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 1));
46 clrbits32((char *) IO_BASE_ADDRESS + 0x698, (1 << 2));
47 clrsetbits32((char *) IO_BASE_ADDRESS + 0x690, 7, (1 << 0));
48}
49
50#define BUNIT_BALIMIT0 0x0b
51#define AUNIT_AVCCTL 0x21
52#define AUNIT_ACFCACV 0x60
53#define CUNIT_ACCESS_CTRL_VIOL 0x41
54#define CUINT_SSA_REGIONAL_TRUNKGATE_CTL 0x43
55#define TUNIT_CTL 0x03
56#define TUNIT_MISC_CTL 0x04
57
58static void ssa_safe_config(void)
59{
60 u32 tmp;
61
62 tmp = iosf_bunit_read(BUNIT_BALIMIT0);
63 iosf_bunit_write(BUNIT_BALIMIT0, (tmp & 0xC0D0D0D0) | 0x1F2F2F2F);
64
65 tmp = iosf_aunit_read(AUNIT_AVCCTL);
66 iosf_aunit_write(AUNIT_AVCCTL, tmp | 0x80000100);
67
68 tmp = iosf_aunit_read(AUNIT_ACFCACV);
69 iosf_aunit_write(AUNIT_ACFCACV, tmp & 0x7FFFFFFF);
70
71 tmp = iosf_cunit_read(CUNIT_ACCESS_CTRL_VIOL);
72 iosf_cunit_write(CUNIT_ACCESS_CTRL_VIOL, tmp & 0x7FFFFFFF);
73
74 iosf_cunit_write(CUINT_SSA_REGIONAL_TRUNKGATE_CTL, 0x70008);
75
76 tmp = iosf_cpu_bus_read(TUNIT_CTL);
77 iosf_cpu_bus_write(TUNIT_CTL, tmp | 0x110430);
78
79 tmp = iosf_cpu_bus_read(TUNIT_MISC_CTL);
80 iosf_cpu_bus_write(TUNIT_MISC_CTL, tmp | 0x40010);
81}
82
83#define R_PCH_PMC_MTPMC1 0xb0
84
85/*
86 * Replacement for refcode.elf
87 */
88void baytrail_run_reference_code(void)
89{
90 u32 tmp;
91 size_t pollcnt;
92
93 printk(BIOS_DEBUG, "ModPHY init entry\n");
94
95 if (pci_read_config8(pcidev_on_root(LPC_DEV, LPC_FUNC), REVID) < RID_B_STEPPING_START) {
96 printk(BIOS_DEBUG, "SOC A0/A1 ModPhy Table programming\n");
97 program_modphy_table(reva0_modphy_table);
98 } else {
99 printk(BIOS_DEBUG, "SOC B0 and later ModPhy Table programming\n");
100 program_modphy_table(revb0_modphy_table);
101 }
102
103 setbits32((char *) PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1, 8);
104
105 for (pollcnt = 0; pollcnt < 10; ++pollcnt) {
106 tmp = read32((char *) PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1);
107 printk(BIOS_DEBUG, "Polling bit3 of R_PCH_PMC_MTPMC1 = %x\n", tmp);
108 if (!(tmp & 8))
109 break;
110 }
111
112 gpio_sc_sdcard_workaround();
113 ssa_safe_config();
114
115 printk(BIOS_DEBUG, "ModPHY init done\n");
116}