blob: 257222fdee53eee634726bdbaee41f0b5edeaa25 [file] [log] [blame]
Nico Huber2a163312020-01-06 17:42:45 +01001/* SPDX-License-Identifier: GPL-2.0-or-later */
2
3#include <stdint.h>
4#include <commonlib/helpers.h>
5#include <device/device.h>
6#include <device/mmio.h>
7#include <device/pci_def.h>
8#include <intelblocks/graphics.h>
9#include <drivers/intel/gma/i915_reg.h>
10
11#include "chip.h"
12
13static void graphics_configure_panelpower(
Michael Niewöhner97e21d32020-12-28 00:49:33 +010014 const struct i915_gpu_panel_config *const panel_cfg,
Nico Huber2a163312020-01-06 17:42:45 +010015 uint8_t *const mmio, const unsigned int panel_idx)
16{
17 const unsigned int offset = panel_idx * 0x100;
18 uint32_t reg32;
19
Michael Niewöhner97e21d32020-12-28 00:49:33 +010020 reg32 = ((DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f) << 4;
Michael Niewöhner8ba96b92020-12-19 22:22:32 +010021 reg32 |= PANEL_POWER_RESET;
Nico Huber2a163312020-01-06 17:42:45 +010022 write32(mmio + PCH_PP_CONTROL + offset, reg32);
23
Michael Niewöhner97e21d32020-12-28 00:49:33 +010024 reg32 = ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16;
25 reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff;
Nico Huber2a163312020-01-06 17:42:45 +010026 write32(mmio + PCH_PP_ON_DELAYS + offset, reg32);
27
Michael Niewöhner97e21d32020-12-28 00:49:33 +010028 reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16;
29 reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff;
Nico Huber2a163312020-01-06 17:42:45 +010030 write32(mmio + PCH_PP_OFF_DELAYS + offset, reg32);
31}
32
33static void graphics_configure_backlight(
Michael Niewöhner97e21d32020-12-28 00:49:33 +010034 const struct i915_gpu_panel_config *const panel_cfg,
Nico Huber2a163312020-01-06 17:42:45 +010035 uint8_t *const mmio, const unsigned int panel_idx)
36{
Michael Niewöhner97e21d32020-12-28 00:49:33 +010037 if (!panel_cfg->backlight_pwm_hz)
Nico Huber2a163312020-01-06 17:42:45 +010038 return;
39
Michael Niewöhner97e21d32020-12-28 00:49:33 +010040 const unsigned int pwm_period = 19200 * 1000 / panel_cfg->backlight_pwm_hz;
Nico Huber2a163312020-01-06 17:42:45 +010041 write32(mmio + BXT_BLC_PWM_FREQ(panel_idx), pwm_period);
42 write32(mmio + BXT_BLC_PWM_DUTY(panel_idx), pwm_period / 2);
43 write32(mmio + BXT_BLC_PWM_CTL(panel_idx),
Michael Niewöhner97e21d32020-12-28 00:49:33 +010044 panel_cfg->backlight_polarity ? BXT_BLC_PWM_POLARITY : 0);
Nico Huber2a163312020-01-06 17:42:45 +010045
46 /* Second backlight control uses display utility pin. */
47 if (panel_idx == 1) {
48 write32(mmio + UTIL_PIN_CTL, 0); /* Make sure it's disabled, don't know
49 what FSP might have done already. */
50 write32(mmio + UTIL_PIN_CTL, UTIL_PIN_MODE_PWM | UTIL_PIN_ENABLE);
51 }
52}
53
Matt DeVillier395ab9d2020-12-23 17:30:27 -060054void graphics_soc_panel_init(struct device *const dev)
Nico Huber2a163312020-01-06 17:42:45 +010055{
56 const struct soc_intel_apollolake_config *const conf = dev->chip_info;
57 const struct resource *mmio_res;
58 void *mmio;
59 unsigned int i;
60
61 /* Some hardware configuration first. */
62
63 if (!conf)
64 return;
65
66 mmio_res = probe_resource(dev, PCI_BASE_ADDRESS_0);
67 if (!mmio_res || !mmio_res->base)
68 return;
69 mmio = (void *)(uintptr_t)mmio_res->base;
70
Michael Niewöhner97e21d32020-12-28 00:49:33 +010071 for (i = 0; i < ARRAY_SIZE(conf->panel_cfg); ++i)
72 graphics_configure_panelpower(&conf->panel_cfg[i], mmio, i);
Nico Huber2a163312020-01-06 17:42:45 +010073
Michael Niewöhner97e21d32020-12-28 00:49:33 +010074 for (i = 0; i < ARRAY_SIZE(conf->panel_cfg); ++i)
75 graphics_configure_backlight(&conf->panel_cfg[i], mmio, i);
Nico Huber2a163312020-01-06 17:42:45 +010076}
Matt DeVillierd7ef4502020-04-21 01:23:10 -050077
78const struct i915_gpu_controller_info *
79intel_igd_get_controller_info(const struct device *device)
80{
81 struct soc_intel_apollolake_config *chip = device->chip_info;
82 return &chip->gfx;
83}