Felix Held | 4a8cd72 | 2020-04-18 22:26:39 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Marshall Dawson | 786bd5d | 2017-06-16 10:10:17 -0600 | [diff] [blame] | 2 | |
Marshall Dawson | 786bd5d | 2017-06-16 10:10:17 -0600 | [diff] [blame] | 3 | #include <cpu/x86/msr.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 4 | #include <cpu/amd/msr.h> |
Marshall Dawson | 786bd5d | 2017-06-16 10:10:17 -0600 | [diff] [blame] | 5 | #include <cpu/x86/tsc.h> |
Marshall Dawson | 786bd5d | 2017-06-16 10:10:17 -0600 | [diff] [blame] | 6 | #include <console/console.h> |
| 7 | #include <soc/pci_devs.h> |
Patrick Rudolph | e56189c | 2018-04-18 10:11:59 +0200 | [diff] [blame] | 8 | #include <device/pci_ops.h> |
Marshall Dawson | 786bd5d | 2017-06-16 10:10:17 -0600 | [diff] [blame] | 9 | |
| 10 | unsigned long tsc_freq_mhz(void) |
| 11 | { |
| 12 | msr_t msr; |
| 13 | uint8_t cpufid; |
| 14 | uint8_t cpudid; |
| 15 | uint8_t boost_states; |
| 16 | |
| 17 | /* |
| 18 | * See the Family 15h Models 70h-7Fh BKDG (PID 55072) definition for |
| 19 | * MSR0000_0010. The TSC increments at the P0 frequency. According |
| 20 | * to the "Software P-state Numbering" section, P0 is the highest |
| 21 | * non-boosted state. freq = 100MHz * (CpuFid + 10h) / (2^(CpuDid)). |
| 22 | */ |
Richard Spiegel | dbd9ea0 | 2018-10-17 09:54:12 -0700 | [diff] [blame] | 23 | boost_states = (pci_read_config32(SOC_PM_DEV, CORE_PERF_BOOST_CTRL) |
Marshall Dawson | 786bd5d | 2017-06-16 10:10:17 -0600 | [diff] [blame] | 24 | >> 2) & 0x7; |
| 25 | |
| 26 | msr = rdmsr(PSTATE_0_MSR + boost_states); |
| 27 | if (!(msr.hi & 0x80000000)) |
| 28 | die("Unknown error: cannot determine P-state 0\n"); |
| 29 | |
| 30 | cpufid = (msr.lo & 0x3f); |
| 31 | cpudid = (msr.lo & 0x1c0) >> 6; |
| 32 | |
| 33 | return (100 * (cpufid + 0x10)) / (0x01 << cpudid); |
| 34 | } |