Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 2 | |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 3 | #include <arch/io.h> |
Felix Held | 3fe1ad1 | 2020-12-09 15:47:59 +0100 | [diff] [blame] | 4 | #include <cf9_reset.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 5 | #include <reset.h> |
Martin Roth | 48e44ee | 2017-11-12 14:54:09 -0700 | [diff] [blame] | 6 | #include <soc/northbridge.h> |
| 7 | #include <soc/pci_devs.h> |
Patrick Rudolph | e56189c | 2018-04-18 10:11:59 +0200 | [diff] [blame] | 8 | #include <device/pci_ops.h> |
Marc Jones | dfeb1c4 | 2017-08-07 19:08:24 -0600 | [diff] [blame] | 9 | #include <soc/southbridge.h> |
Marshall Dawson | 69486ca | 2019-05-02 12:03:45 -0600 | [diff] [blame] | 10 | #include <amdblocks/acpimmio.h> |
Nico Huber | 73c1119 | 2018-10-06 18:20:47 +0200 | [diff] [blame] | 11 | #include <amdblocks/reset.h> |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 12 | |
Marshall Dawson | 2e49cf12 | 2018-08-03 17:05:22 -0600 | [diff] [blame] | 13 | void set_warm_reset_flag(void) |
| 14 | { |
| 15 | u32 htic; |
| 16 | htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL); |
| 17 | htic |= HTIC_COLD_RST_DET; |
| 18 | pci_write_config32(SOC_HT_DEV, HT_INIT_CONTROL, htic); |
| 19 | } |
| 20 | |
| 21 | int is_warm_reset(void) |
| 22 | { |
| 23 | u32 htic; |
| 24 | htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL); |
| 25 | return !!(htic & HTIC_COLD_RST_DET); |
| 26 | } |
| 27 | |
Martin Roth | 48e44ee | 2017-11-12 14:54:09 -0700 | [diff] [blame] | 28 | /* Clear bits 5, 9 & 10, used to signal the reset type */ |
| 29 | static void clear_bios_reset(void) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 30 | { |
| 31 | u32 htic; |
Martin Roth | 48e44ee | 2017-11-12 14:54:09 -0700 | [diff] [blame] | 32 | htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL); |
| 33 | htic &= ~HTIC_BIOSR_DETECT; |
| 34 | pci_write_config32(SOC_HT_DEV, HT_INIT_CONTROL, htic); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 35 | } |
| 36 | |
Nico Huber | 73c1119 | 2018-10-06 18:20:47 +0200 | [diff] [blame] | 37 | void do_cold_reset(void) |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 38 | { |
Martin Roth | 48e44ee | 2017-11-12 14:54:09 -0700 | [diff] [blame] | 39 | clear_bios_reset(); |
| 40 | |
| 41 | /* De-assert and then assert all PwrGood signals on CF9 reset. */ |
| 42 | pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | |
| 43 | TOGGLE_ALL_PWR_GOOD); |
Felix Held | 3fe1ad1 | 2020-12-09 15:47:59 +0100 | [diff] [blame] | 44 | outb(RST_CPU | SYS_RST, RST_CNT); |
Martin Roth | 48e44ee | 2017-11-12 14:54:09 -0700 | [diff] [blame] | 45 | } |
| 46 | |
Nico Huber | 73c1119 | 2018-10-06 18:20:47 +0200 | [diff] [blame] | 47 | void do_warm_reset(void) |
Martin Roth | 48e44ee | 2017-11-12 14:54:09 -0700 | [diff] [blame] | 48 | { |
Marshall Dawson | 2e49cf12 | 2018-08-03 17:05:22 -0600 | [diff] [blame] | 49 | set_warm_reset_flag(); |
Martin Roth | 48e44ee | 2017-11-12 14:54:09 -0700 | [diff] [blame] | 50 | clear_bios_reset(); |
| 51 | |
| 52 | /* Assert reset signals only. */ |
Felix Held | 3fe1ad1 | 2020-12-09 15:47:59 +0100 | [diff] [blame] | 53 | outb(RST_CPU | SYS_RST, RST_CNT); |
Marc Jones | 2448484 | 2017-05-04 21:17:45 -0600 | [diff] [blame] | 54 | } |
Nico Huber | 73c1119 | 2018-10-06 18:20:47 +0200 | [diff] [blame] | 55 | |
| 56 | void do_board_reset(void) |
| 57 | { |
| 58 | /* TODO: Would a warm_reset() suffice? */ |
| 59 | do_cold_reset(); |
| 60 | } |