Felix Held | dba3229 | 2020-03-31 23:54:44 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Felix Held | dba3229 | 2020-03-31 23:54:44 +0200 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/pci_ops.h> |
| 5 | #include <device/pci_def.h> |
Felix Held | 285dd6e | 2021-02-17 22:16:40 +0100 | [diff] [blame] | 6 | #include <cpu/amd/msr.h> |
Felix Held | dba3229 | 2020-03-31 23:54:44 +0200 | [diff] [blame] | 7 | #include <cpu/x86/msr.h> |
| 8 | #include <soc/pci_devs.h> |
| 9 | #include <soc/northbridge.h> |
| 10 | #include <soc/southbridge.h> |
| 11 | #include <amdblocks/psp.h> |
| 12 | |
| 13 | void soc_enable_psp_early(void) |
| 14 | { |
Elyes HAOUAS | b30d054 | 2020-04-28 09:42:47 +0200 | [diff] [blame] | 15 | u32 base, limit; |
| 16 | u16 cmd; |
Felix Held | dba3229 | 2020-03-31 23:54:44 +0200 | [diff] [blame] | 17 | |
| 18 | /* Open a posted hole from 0x80000000 : 0xfed00000-1 */ |
| 19 | base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE; |
| 20 | limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8); |
| 21 | pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit); |
| 22 | pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base); |
| 23 | |
| 24 | /* Preload a value into BAR and enable it */ |
| 25 | pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE); |
| 26 | pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN); |
| 27 | |
| 28 | /* Enable memory access and master */ |
Elyes HAOUAS | b30d054 | 2020-04-28 09:42:47 +0200 | [diff] [blame] | 29 | cmd = pci_read_config16(SOC_PSP_DEV, PCI_COMMAND); |
Felix Held | dba3229 | 2020-03-31 23:54:44 +0200 | [diff] [blame] | 30 | cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; |
Elyes HAOUAS | b30d054 | 2020-04-28 09:42:47 +0200 | [diff] [blame] | 31 | pci_write_config16(SOC_PSP_DEV, PCI_COMMAND, cmd); |
Felix Held | dba3229 | 2020-03-31 23:54:44 +0200 | [diff] [blame] | 32 | }; |
| 33 | |
Marshall Dawson | d6b7236 | 2020-03-05 11:44:24 -0700 | [diff] [blame] | 34 | void *soc_get_mbox_address(void) |
Felix Held | dba3229 | 2020-03-31 23:54:44 +0200 | [diff] [blame] | 35 | { |
| 36 | uintptr_t psp_mmio; |
| 37 | |
| 38 | /* Check for presence of the PSP */ |
| 39 | if (pci_read_config32(SOC_PSP_DEV, PCI_VENDOR_ID) == 0xffffffff) { |
| 40 | printk(BIOS_WARNING, "PSP: No SOC_PSP_DEV found at D%xF%x\n", |
| 41 | PSP_DEV, PSP_FUNC); |
| 42 | return 0; |
| 43 | } |
| 44 | |
| 45 | /* Determine if Bar3Hide has been set, and if hidden get the base from |
| 46 | * the MSR instead. */ |
| 47 | if (pci_read_config32(SOC_PSP_DEV, PSP_BAR_ENABLES) & BAR3HIDE) { |
Felix Held | e09294f | 2021-02-17 22:22:21 +0100 | [diff] [blame] | 48 | psp_mmio = rdmsr(PSP_ADDR_MSR).lo; |
Felix Held | 31fdefe | 2021-01-29 22:33:17 +0100 | [diff] [blame] | 49 | if (!psp_mmio) { |
Felix Held | e09294f | 2021-02-17 22:22:21 +0100 | [diff] [blame] | 50 | printk(BIOS_WARNING, "PSP: BAR hidden, PSP_ADDR_MSR uninitialized\n"); |
Felix Held | dba3229 | 2020-03-31 23:54:44 +0200 | [diff] [blame] | 51 | return 0; |
| 52 | } |
| 53 | } else { |
| 54 | psp_mmio = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4) & |
| 55 | ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; |
| 56 | } |
| 57 | |
Marshall Dawson | d6b7236 | 2020-03-05 11:44:24 -0700 | [diff] [blame] | 58 | return (void *)(psp_mmio + PSP_MAILBOX_OFFSET); |
Felix Held | dba3229 | 2020-03-31 23:54:44 +0200 | [diff] [blame] | 59 | } |