Furquan Shaikh | cff479e | 2020-07-08 15:47:19 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
Raul E Rangel | 4e80fae | 2020-12-16 10:08:41 -0700 | [diff] [blame] | 3 | #include <amdblocks/amd_pci_util.h> |
Furquan Shaikh | cff479e | 2020-07-08 15:47:19 -0700 | [diff] [blame] | 4 | #include <soc/pci_devs.h> |
Furquan Shaikh | cff479e | 2020-07-08 15:47:19 -0700 | [diff] [blame] | 5 | |
Raul E Rangel | a8405a4 | 2021-05-07 11:19:42 -0600 | [diff] [blame] | 6 | /* See AMD PPR 55570 - IOAPIC Initialization for the table that AGESA sets up */ |
| 7 | const struct pci_routing_info pci_routing_table[] = { |
| 8 | {PCIE_GPP_0_DEVFN, 0, PCI_SWIZZLE_ABCD, 0x10}, |
| 9 | {PCIE_GPP_1_DEVFN, 1, PCI_SWIZZLE_ABCD, 0x11}, |
| 10 | {PCIE_GPP_2_DEVFN, 2, PCI_SWIZZLE_ABCD, 0x12}, |
| 11 | {PCIE_GPP_3_DEVFN, 3, PCI_SWIZZLE_ABCD, 0x13}, |
| 12 | {PCIE_GPP_4_DEVFN, 4, PCI_SWIZZLE_ABCD, 0x10}, |
| 13 | {PCIE_GPP_5_DEVFN, 5, PCI_SWIZZLE_ABCD, 0x11}, |
| 14 | {PCIE_GPP_6_DEVFN, 6, PCI_SWIZZLE_ABCD, 0x12}, |
| 15 | {PCIE_GPP_A_DEVFN, 7, PCI_SWIZZLE_ABCD, 0x13}, |
| 16 | {PCIE_GPP_B_DEVFN, 7, PCI_SWIZZLE_CDAB, 0x0C}, |
Raul E Rangel | 2f5fd11 | 2020-12-14 16:55:09 -0700 | [diff] [blame] | 17 | }; |
| 18 | |
Raul E Rangel | a8405a4 | 2021-05-07 11:19:42 -0600 | [diff] [blame] | 19 | const struct pci_routing_info *get_pci_routing_table(size_t *entries) |
| 20 | { |
| 21 | *entries = ARRAY_SIZE(pci_routing_table); |
| 22 | return pci_routing_table; |
| 23 | } |