Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 2 | |
Angel Pons | 6237175 | 2021-03-27 21:13:44 +0100 | [diff] [blame] | 3 | #ifndef NORTHBRIDGE_INTEL_HASWELL_HASWELL_H |
| 4 | #define NORTHBRIDGE_INTEL_HASWELL_HASWELL_H |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 5 | |
Angel Pons | 9fa1418 | 2021-03-27 20:32:16 +0100 | [diff] [blame] | 6 | #include <device/device.h> |
| 7 | #include <northbridge/intel/common/fixed_bars.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 8 | |
Angel Pons | a3cb322 | 2020-09-14 13:15:19 +0200 | [diff] [blame] | 9 | #include "memmap.h" |
Angel Pons | 9fa1418 | 2021-03-27 20:32:16 +0100 | [diff] [blame] | 10 | #include "registers/dmibar.h" |
| 11 | #include "registers/epbar.h" |
| 12 | #include "registers/host_bridge.h" |
| 13 | #include "registers/mchbar.h" |
Angel Pons | d6c4538 | 2021-03-27 21:24:57 +0100 | [diff] [blame] | 14 | #include "registers/pcie_graphics.h" |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 15 | |
| 16 | /* Device 0:0.0 PCI configuration space (Host Bridge) */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 17 | #define HOST_BRIDGE PCI_DEV(0, 0, 0) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 18 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 19 | /* Device 0:2.0 PCI configuration space (Graphics Device) */ |
| 20 | |
| 21 | #define MSAC 0x62 /* Multi Size Aperture Control */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 22 | |
Angel Pons | e220e31 | 2020-07-22 00:55:38 +0200 | [diff] [blame] | 23 | #define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ |
| 24 | #define DMAR_LCKDN (1 << 31) |
| 25 | #define SPCAPCTRL (1 << 25) |
| 26 | #define L3HIT2PEND_DIS (1 << 20) |
| 27 | #define PRSCAPDIS (1 << 2) |
| 28 | #define GLBIOTLBINV (1 << 1) |
| 29 | #define GLBCTXTINV (1 << 0) |
| 30 | |
Angel Pons | 73fa035 | 2020-07-03 12:29:03 +0200 | [diff] [blame] | 31 | void mb_late_romstage_setup(void); /* optional */ |
Angel Pons | 2e25ac6 | 2020-07-03 12:06:04 +0200 | [diff] [blame] | 32 | |
Angel Pons | e816829 | 2020-07-03 11:42:22 +0200 | [diff] [blame] | 33 | void haswell_early_initialization(void); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 34 | void haswell_late_initialization(void); |
Tristan Corrick | 334be32 | 2018-12-17 22:10:21 +1300 | [diff] [blame] | 35 | void haswell_unhide_peg(void); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 36 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 37 | void report_platform_info(void); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 38 | |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 39 | struct acpi_rsdp; |
Furquan Shaikh | 0f007d8 | 2020-04-24 06:41:18 -0700 | [diff] [blame] | 40 | unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start, |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 41 | struct acpi_rsdp *rsdp); |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 42 | |
Angel Pons | 6237175 | 2021-03-27 21:13:44 +0100 | [diff] [blame] | 43 | #endif /* NORTHBRIDGE_INTEL_HASWELL_HASWELL_H */ |