Angel Pons | d32b6de | 2020-04-03 01:23:13 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 2 | |
Kyösti Mälkki | e3ddee0 | 2014-05-03 10:45:28 +0300 | [diff] [blame] | 3 | #include <bootmode.h> |
Kyösti Mälkki | 17887d0 | 2019-07-23 19:08:01 +0300 | [diff] [blame] | 4 | #include <boot/coreboot_tables.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 6 | #include <device/device.h> |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 7 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 8 | #include <southbridge/intel/bd82x6x/pch.h> |
Patrick Rudolph | e8e66f4 | 2016-02-06 17:42:42 +0100 | [diff] [blame] | 9 | #include <southbridge/intel/common/gpio.h> |
Aaron Durbin | b0f8151 | 2016-07-25 21:31:41 -0500 | [diff] [blame] | 10 | #include <vendorcode/google/chromeos/chromeos.h> |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 11 | |
| 12 | #define GPIO_SPI_WP 24 |
| 13 | #define GPIO_REC_MODE 42 |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 14 | |
| 15 | #define FLAG_SPI_WP 0 |
| 16 | #define FLAG_REC_MODE 1 |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 17 | |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 18 | #include "ec.h" |
| 19 | #include <ec/smsc/mec1308/ec.h> |
| 20 | |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 21 | void fill_lb_gpios(struct lb_gpios *gpios) |
| 22 | { |
Elyes HAOUAS | a4faec3 | 2020-04-22 16:49:28 +0200 | [diff] [blame] | 23 | const pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); |
Kyösti Mälkki | 17887d0 | 2019-07-23 19:08:01 +0300 | [diff] [blame] | 24 | u16 gen_pmcon_1 = pci_s_read_config32(dev, GEN_PMCON_1); |
Joel Kitching | 2e1f655 | 2019-03-23 12:41:04 +0800 | [diff] [blame] | 25 | u8 lid = ec_read(0x83); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 26 | |
Joel Kitching | 2e1f655 | 2019-03-23 12:41:04 +0800 | [diff] [blame] | 27 | struct lb_gpio chromeos_gpios[] = { |
Joel Kitching | 2e1f655 | 2019-03-23 12:41:04 +0800 | [diff] [blame] | 28 | /* Recovery: GPIO42 = CHP3_REC_MODE# */ |
| 29 | {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), |
Matt Delco | 2cb3996 | 2019-04-30 14:59:43 -0700 | [diff] [blame] | 30 | "presence"}, |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 31 | |
Joel Kitching | 2e1f655 | 2019-03-23 12:41:04 +0800 | [diff] [blame] | 32 | {100, ACTIVE_HIGH, lid & 1, "lid"}, |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 33 | |
Joel Kitching | 2e1f655 | 2019-03-23 12:41:04 +0800 | [diff] [blame] | 34 | /* Power Button */ |
| 35 | {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"}, |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 36 | |
Joel Kitching | 2e1f655 | 2019-03-23 12:41:04 +0800 | [diff] [blame] | 37 | /* Did we load the VGA Option ROM? */ |
| 38 | /* -1 indicates that this is a pseudo GPIO */ |
| 39 | {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, |
| 40 | }; |
| 41 | lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 42 | } |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 43 | |
Patrick Georgi | 961e8a4 | 2015-06-30 12:49:50 +0200 | [diff] [blame] | 44 | int get_write_protect_state(void) |
| 45 | { |
Elyes HAOUAS | a4faec3 | 2020-04-22 16:49:28 +0200 | [diff] [blame] | 46 | const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); |
Kyösti Mälkki | 17887d0 | 2019-07-23 19:08:01 +0300 | [diff] [blame] | 47 | return (pci_s_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; |
Patrick Georgi | 961e8a4 | 2015-06-30 12:49:50 +0200 | [diff] [blame] | 48 | } |
| 49 | |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 50 | int get_recovery_mode_switch(void) |
| 51 | { |
Elyes HAOUAS | a4faec3 | 2020-04-22 16:49:28 +0200 | [diff] [blame] | 52 | const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); |
Kyösti Mälkki | 17887d0 | 2019-07-23 19:08:01 +0300 | [diff] [blame] | 53 | return (pci_s_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 54 | } |
| 55 | |
Kyösti Mälkki | e3ddee0 | 2014-05-03 10:45:28 +0300 | [diff] [blame] | 56 | void init_bootmode_straps(void) |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 57 | { |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 58 | u32 flags = 0; |
Elyes HAOUAS | a4faec3 | 2020-04-22 16:49:28 +0200 | [diff] [blame] | 59 | const pci_devfn_t dev = PCI_DEV(0, 0x1f, 2); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 60 | |
| 61 | /* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */ |
Patrick Rudolph | e8e66f4 | 2016-02-06 17:42:42 +0100 | [diff] [blame] | 62 | if (get_gpio(GPIO_SPI_WP)) |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 63 | flags |= (1 << FLAG_SPI_WP); |
| 64 | /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ |
Patrick Rudolph | e8e66f4 | 2016-02-06 17:42:42 +0100 | [diff] [blame] | 65 | if (!get_gpio(GPIO_REC_MODE)) |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 66 | flags |= (1 << FLAG_REC_MODE); |
Stefan Reinauer | 155e9b5 | 2012-04-27 23:19:58 +0200 | [diff] [blame] | 67 | |
Kyösti Mälkki | 17887d0 | 2019-07-23 19:08:01 +0300 | [diff] [blame] | 68 | pci_s_write_config32(dev, SATA_SP, flags); |
Kyösti Mälkki | e3ddee0 | 2014-05-03 10:45:28 +0300 | [diff] [blame] | 69 | } |
Aaron Durbin | b0f8151 | 2016-07-25 21:31:41 -0500 | [diff] [blame] | 70 | |
| 71 | static const struct cros_gpio cros_gpios[] = { |
| 72 | CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME), |
Aaron Durbin | b0f8151 | 2016-07-25 21:31:41 -0500 | [diff] [blame] | 73 | CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME), |
| 74 | }; |
| 75 | |
| 76 | void mainboard_chromeos_acpi_generate(void) |
| 77 | { |
Kyösti Mälkki | bc441c7 | 2021-02-18 06:26:52 +0200 | [diff] [blame] | 78 | if (CONFIG(CHROMEOS_NVS) && ec_read(0xcb)) |
| 79 | chromeos_set_ecfw_rw(); |
| 80 | |
Aaron Durbin | b0f8151 | 2016-07-25 21:31:41 -0500 | [diff] [blame] | 81 | chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios)); |
| 82 | } |