Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 2 | |
| 3 | #include <cbmem.h> |
| 4 | #include <console/console.h> |
Elyes HAOUAS | 32da343 | 2020-05-17 17:15:31 +0200 | [diff] [blame] | 5 | #include <cpu/x86/lapic_def.h> |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 6 | #include <device/pci.h> |
| 7 | #include <device/pci_ids.h> |
Marc Jones | 521a03f | 2020-10-19 13:46:59 -0600 | [diff] [blame] | 8 | #include <soc/acpi.h> |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 9 | #include <soc/iomap.h> |
| 10 | #include <soc/pci_devs.h> |
| 11 | #include <soc/ramstage.h> |
Andrey Petrov | 662da6c | 2020-03-16 22:46:57 -0700 | [diff] [blame] | 12 | #include <soc/util.h> |
| 13 | #include <fsp/util.h> |
Arthur Heymans | 77509be | 2020-10-22 17:11:22 +0200 | [diff] [blame] | 14 | #include <security/intel/txt/txt_platform.h> |
Arthur Heymans | 9d8a455 | 2021-02-02 19:21:24 +0100 | [diff] [blame] | 15 | #include <security/intel/txt/txt.h> |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 16 | |
| 17 | struct map_entry { |
| 18 | uint32_t reg; |
| 19 | int is_64_bit; |
| 20 | int is_limit; |
| 21 | int mask_bits; |
| 22 | const char *description; |
| 23 | }; |
| 24 | |
| 25 | enum { |
| 26 | TOHM_REG, |
| 27 | MMIOL_REG, |
| 28 | MMCFG_BASE_REG, |
| 29 | MMCFG_LIMIT_REG, |
| 30 | TOLM_REG, |
| 31 | ME_BASE_REG, |
| 32 | ME_LIMIT_REG, |
| 33 | TSEG_BASE_REG, |
| 34 | TSEG_LIMIT_REG, |
| 35 | /* Must be last. */ |
| 36 | NUM_MAP_ENTRIES |
| 37 | }; |
| 38 | |
| 39 | static struct map_entry memory_map[NUM_MAP_ENTRIES] = { |
| 40 | [TOHM_REG] = MAP_ENTRY_LIMIT_64(VTD_TOHM_CSR, 26, "TOHM"), |
| 41 | [MMIOL_REG] = MAP_ENTRY_BASE_32(VTD_MMIOL_CSR, "MMIOL"), |
| 42 | [MMCFG_BASE_REG] = MAP_ENTRY_BASE_64(VTD_MMCFG_BASE_CSR, "MMCFG_BASE"), |
| 43 | [MMCFG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(VTD_MMCFG_LIMIT_CSR, 26, "MMCFG_LIMIT"), |
| 44 | [TOLM_REG] = MAP_ENTRY_LIMIT_32(VTD_TOLM_CSR, 26, "TOLM"), |
| 45 | [ME_BASE_REG] = MAP_ENTRY_BASE_64(VTD_ME_BASE_CSR, "ME_BASE"), |
| 46 | [ME_LIMIT_REG] = MAP_ENTRY_LIMIT_64(VTD_ME_LIMIT_CSR, 19, "ME_LIMIT"), |
| 47 | [TSEG_BASE_REG] = MAP_ENTRY_BASE_32(VTD_TSEG_BASE_CSR, "TSEGMB_BASE"), |
| 48 | [TSEG_LIMIT_REG] = MAP_ENTRY_LIMIT_32(VTD_TSEG_LIMIT_CSR, 20, "TSEGMB_LIMIT"), |
| 49 | }; |
| 50 | |
| 51 | static void read_map_entry(struct device *dev, struct map_entry *entry, |
| 52 | uint64_t *result) |
| 53 | { |
| 54 | uint64_t value; |
| 55 | uint64_t mask; |
| 56 | |
| 57 | /* All registers are on a 1MiB granularity. */ |
| 58 | mask = ((1ULL << entry->mask_bits) - 1); |
| 59 | mask = ~mask; |
| 60 | |
| 61 | value = 0; |
| 62 | |
| 63 | if (entry->is_64_bit) { |
| 64 | value = pci_read_config32(dev, entry->reg + sizeof(uint32_t)); |
| 65 | value <<= 32; |
| 66 | } |
| 67 | |
| 68 | value |= (uint64_t)pci_read_config32(dev, entry->reg); |
| 69 | value &= mask; |
| 70 | |
| 71 | if (entry->is_limit) |
| 72 | value |= ~mask; |
| 73 | |
| 74 | *result = value; |
| 75 | } |
| 76 | |
| 77 | static void mc_read_map_entries(struct device *dev, uint64_t *values) |
| 78 | { |
| 79 | int i; |
| 80 | for (i = 0; i < NUM_MAP_ENTRIES; i++) |
| 81 | read_map_entry(dev, &memory_map[i], &values[i]); |
| 82 | } |
| 83 | |
| 84 | static void mc_report_map_entries(struct device *dev, uint64_t *values) |
| 85 | { |
| 86 | int i; |
| 87 | for (i = 0; i < NUM_MAP_ENTRIES; i++) { |
| 88 | printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", |
| 89 | memory_map[i].description, values[i]); |
| 90 | } |
| 91 | } |
| 92 | |
Arthur Heymans | 77509be | 2020-10-22 17:11:22 +0200 | [diff] [blame] | 93 | static void configure_dpr(struct device *dev) |
| 94 | { |
| 95 | const uintptr_t cbmem_top_mb = ALIGN_UP((uintptr_t)cbmem_top(), MiB) / MiB; |
| 96 | union dpr_register dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) }; |
| 97 | |
| 98 | /* The DPR lock bit has to be set sufficiently early. It looks like |
| 99 | * it cannot be set anymore after FSP-S. |
| 100 | */ |
| 101 | dpr.lock = 1; |
| 102 | dpr.epm = 1; |
| 103 | dpr.size = dpr.top - cbmem_top_mb; |
| 104 | pci_write_config32(dev, VTD_LTDPR, dpr.raw); |
| 105 | } |
| 106 | |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 107 | /* |
| 108 | * Host Memory Map: |
| 109 | * |
| 110 | * +--------------------------+ TOCM (2 pow 46 - 1) |
| 111 | * | Reserved | |
| 112 | * +--------------------------+ |
| 113 | * | MMIOH (relocatable) | |
| 114 | * +--------------------------+ |
| 115 | * | PCISeg | |
| 116 | * +--------------------------+ TOHM |
| 117 | * | High DRAM Memory | |
| 118 | * +--------------------------+ 4GiB (0x100000000) |
| 119 | * +--------------------------+ 0xFFFF_FFFF |
| 120 | * | Firmware | |
| 121 | * +--------------------------+ 0xFF00_0000 |
| 122 | * | Reserved | |
| 123 | * +--------------------------+ 0xFEF0_0000 |
| 124 | * | Local xAPIC | |
| 125 | * +--------------------------+ 0xFEE0_0000 |
| 126 | * | HPET/LT/TPM/Others | |
| 127 | * +--------------------------+ 0xFED0_0000 |
| 128 | * | I/O xAPIC | |
| 129 | * +--------------------------+ 0xFEC0_0000 |
| 130 | * | Reserved | |
| 131 | * +--------------------------+ 0xFEB8_0000 |
| 132 | * | Reserved | |
| 133 | * +--------------------------+ 0xFEB0_0000 |
| 134 | * | Reserved | |
| 135 | * +--------------------------+ 0xFE00_0000 |
| 136 | * | MMIOL (relocatable) | |
| 137 | * | P2SB PCR cfg BAR | (0xfd000000 - 0xfdffffff |
| 138 | * | BAR space | [mem 0x90000000-0xfcffffff] available for PCI devices |
| 139 | * +--------------------------+ 0x9000_0000 |
| 140 | * |PCIe MMCFG (relocatable) | CONFIG_MMCONF_BASE_ADDRESS 64 or 256MB |
| 141 | * | | (0x80000000 - 0x8fffffff, 0x40000) |
| 142 | * +--------------------------+ TOLM |
| 143 | * | MEseg (relocatable) | 32, 64, 128 or 256 MB (0x78000000 - 0x7fffffff, 0x20000) |
| 144 | * +--------------------------+ |
| 145 | * | Tseg (relocatable) | N x 8MB (0x70000000 - 0x77ffffff, 0x20000) |
Arthur Heymans | 77509be | 2020-10-22 17:11:22 +0200 | [diff] [blame] | 146 | * +--------------------------+ |
| 147 | * | DPR | |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 148 | * +--------------------------+ cbmem_top |
| 149 | * | Reserved - CBMEM | (0x6fffe000 - 0x6fffffff, 0x2000) |
| 150 | * +--------------------------+ |
| 151 | * | Reserved - FSP | (0x6fbfe000 - 0x6fffdfff, 0x400000) |
| 152 | * +--------------------------+ top_of_ram (0x6fbfdfff) |
| 153 | * | Low DRAM Memory | |
| 154 | * +--------------------------+ FFFFF (1MB) |
| 155 | * | E & F segments | |
| 156 | * +--------------------------+ E0000 |
| 157 | * | C & D segments | |
| 158 | * +--------------------------+ C0000 |
| 159 | * | VGA & SMM Memory | |
| 160 | * +--------------------------+ A0000 |
| 161 | * | Conventional Memory | |
| 162 | * | (DOS Range) | |
| 163 | * +--------------------------+ 0 |
| 164 | */ |
| 165 | |
| 166 | static void mc_add_dram_resources(struct device *dev, int *res_count) |
| 167 | { |
| 168 | struct range_entry fsp_mem; |
| 169 | uint64_t base_kb; |
| 170 | uint64_t size_kb; |
| 171 | uint64_t top_of_ram; |
| 172 | uint64_t mc_values[NUM_MAP_ENTRIES]; |
| 173 | struct resource *resource; |
| 174 | int index = *res_count; |
| 175 | |
Marc Jones | 662ac54 | 2020-11-02 21:26:41 -0700 | [diff] [blame] | 176 | /* Only add dram resources once. */ |
| 177 | if (dev->bus->secondary != 0) |
| 178 | return; |
| 179 | |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 180 | fsp_find_reserved_memory(&fsp_mem); |
| 181 | |
| 182 | /* Read in the MAP registers and report their values. */ |
| 183 | mc_read_map_entries(dev, &mc_values[0]); |
| 184 | mc_report_map_entries(dev, &mc_values[0]); |
| 185 | |
| 186 | top_of_ram = range_entry_base(&fsp_mem) - 1; |
| 187 | printk(BIOS_SPEW, "cbmem_top: 0x%lx, fsp range: [0x%llx - 0x%llx], top_of_ram: 0x%llx\n", |
| 188 | (uintptr_t) cbmem_top(), range_entry_base(&fsp_mem), |
| 189 | range_entry_end(&fsp_mem), top_of_ram); |
| 190 | |
| 191 | /* Conventional Memory (DOS region, 0x0 to 0x9FFFF) */ |
| 192 | base_kb = 0; |
| 193 | size_kb = (0xa0000 >> 10); |
| 194 | LOG_MEM_RESOURCE("legacy_ram", dev, index, base_kb, size_kb); |
| 195 | ram_resource(dev, index++, base_kb, size_kb); |
| 196 | |
| 197 | /* 1MB -> top_of_ram i.e., fsp_mem_base+1*/ |
| 198 | base_kb = (0x100000 >> 10); |
| 199 | size_kb = (top_of_ram - 0xfffff) >> 10; |
| 200 | LOG_MEM_RESOURCE("low_ram", dev, index, base_kb, size_kb); |
| 201 | ram_resource(dev, index++, base_kb, size_kb); |
| 202 | |
Arthur Heymans | c2503db | 2020-11-23 15:45:00 +0100 | [diff] [blame] | 203 | /* fsp_mem_base -> cbmem_top */ |
| 204 | base_kb = top_of_ram / KiB; |
| 205 | size_kb = ((uintptr_t)cbmem_top() - top_of_ram) / KiB; |
| 206 | reserved_ram_resource(dev, index++, base_kb, size_kb); |
| 207 | |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 208 | /* |
| 209 | * FSP meomoy, CBMem regions are already added as reserved |
| 210 | * Add TSEG and MESEG Regions as reserved memory |
| 211 | * src/drivers/intel/fsp2_0/memory_init.c sets CBMEM reserved size |
| 212 | * arch_upd->BootLoaderTolumSize = cbmem_overhead_size(); == 2 * CBMEM_ROOT_MIN_SIZE |
| 213 | * typically 0x2000 |
| 214 | * Example config: |
| 215 | * FSP_RESERVED_MEMORY_RESOURCE_HOB |
| 216 | * FspReservedMemoryResource Base : 6FBFE000 |
| 217 | * FspReservedMemoryResource Size : 400000 |
| 218 | * FSP_BOOT_LOADER_TOLUM_HOB |
| 219 | * FspBootLoaderTolum Base : 6FFFE000 |
| 220 | * FspBootLoaderTolum Size : 2000 |
| 221 | */ |
| 222 | |
| 223 | /* Mark TSEG/SMM region as reserved */ |
| 224 | base_kb = (mc_values[TSEG_BASE_REG] >> 10); |
| 225 | size_kb = (mc_values[TSEG_LIMIT_REG] - mc_values[TSEG_BASE_REG] + 1) >> 10; |
| 226 | LOG_MEM_RESOURCE("mmio_tseg", dev, index, base_kb, size_kb); |
| 227 | reserved_ram_resource(dev, index++, base_kb, size_kb); |
| 228 | |
Arthur Heymans | 77509be | 2020-10-22 17:11:22 +0200 | [diff] [blame] | 229 | /* Reserve and set up DPR */ |
| 230 | configure_dpr(dev); |
| 231 | union dpr_register dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) }; |
| 232 | if (dpr.size) { |
Arthur Heymans | 08d8dd3 | 2020-12-16 14:29:24 +0100 | [diff] [blame] | 233 | uint64_t dpr_base_k = (dpr.top - dpr.size) << 10; |
| 234 | uint64_t dpr_size_k = dpr.size << 10; |
Arthur Heymans | 77509be | 2020-10-22 17:11:22 +0200 | [diff] [blame] | 235 | reserved_ram_resource(dev, index++, dpr_base_k, dpr_size_k); |
| 236 | LOG_MEM_RESOURCE("dpr", dev, index, dpr_base_k, dpr_size_k); |
| 237 | } |
| 238 | |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 239 | /* Mark region between TSEG - TOLM (eg. MESEG) as reserved */ |
| 240 | if (mc_values[TSEG_LIMIT_REG] < mc_values[TOLM_REG]) { |
| 241 | base_kb = ((mc_values[TSEG_LIMIT_REG] + 1) >> 10); |
| 242 | size_kb = (mc_values[TOLM_REG] - mc_values[TSEG_LIMIT_REG]) >> 10; |
| 243 | LOG_MEM_RESOURCE("mmio_tolm", dev, index, base_kb, size_kb); |
| 244 | reserved_ram_resource(dev, index++, base_kb, size_kb); |
| 245 | } |
| 246 | |
| 247 | /* 4GiB -> TOHM */ |
| 248 | if (mc_values[TOHM_REG] > 0x100000000) { |
| 249 | base_kb = (0x100000000 >> 10); |
| 250 | size_kb = (mc_values[TOHM_REG] - 0x100000000 + 1) >> 10; |
| 251 | LOG_MEM_RESOURCE("high_ram", dev, index, base_kb, size_kb); |
| 252 | ram_resource(dev, index++, base_kb, size_kb); |
| 253 | } |
| 254 | |
| 255 | /* add MMIO CFG resource */ |
| 256 | resource = new_resource(dev, index++); |
| 257 | resource->base = (resource_t) mc_values[MMCFG_BASE_REG]; |
| 258 | resource->size = (resource_t) (mc_values[MMCFG_LIMIT_REG] - |
| 259 | mc_values[MMCFG_BASE_REG] + 1); |
| 260 | resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | |
| 261 | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; |
| 262 | LOG_MEM_RESOURCE("mmiocfg_res", dev, index-1, (resource->base >> 10), |
| 263 | (resource->size >> 10)); |
| 264 | |
| 265 | /* add Local APIC resource */ |
| 266 | resource = new_resource(dev, index++); |
| 267 | resource->base = LAPIC_DEFAULT_BASE; |
| 268 | resource->size = 0x00001000; |
| 269 | resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | |
| 270 | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; |
| 271 | LOG_MEM_RESOURCE("apic_res", dev, index-1, (resource->base >> 10), |
| 272 | (resource->size >> 10)); |
| 273 | |
| 274 | /* |
| 275 | * Add legacy region as reserved - 0xa000 - 1MB |
| 276 | * Reserve everything between A segment and 1MB: |
| 277 | * |
| 278 | * 0xa0000 - 0xbffff: legacy VGA |
| 279 | * 0xc0000 - 0xfffff: RAM |
| 280 | */ |
| 281 | base_kb = VGA_BASE_ADDRESS >> 10; |
| 282 | size_kb = VGA_BASE_SIZE >> 10; |
| 283 | LOG_MEM_RESOURCE("legacy_mmio", dev, index, base_kb, size_kb); |
| 284 | mmio_resource(dev, index++, base_kb, size_kb); |
| 285 | |
| 286 | base_kb = (0xc0000 >> 10); |
| 287 | size_kb = (0x100000 - 0xc0000) >> 10; |
| 288 | LOG_MEM_RESOURCE("legacy_write_protect", dev, index, base_kb, size_kb); |
| 289 | reserved_ram_resource(dev, index++, base_kb, size_kb); |
| 290 | |
| 291 | *res_count = index; |
| 292 | } |
| 293 | |
| 294 | static void mmapvtd_read_resources(struct device *dev) |
| 295 | { |
| 296 | int index = 0; |
| 297 | |
| 298 | /* Read standard PCI resources. */ |
| 299 | pci_dev_read_resources(dev); |
| 300 | |
| 301 | /* Calculate and add DRAM resources. */ |
| 302 | mc_add_dram_resources(dev, &index); |
| 303 | } |
| 304 | |
| 305 | static void mmapvtd_init(struct device *dev) |
| 306 | { |
| 307 | } |
| 308 | |
| 309 | static struct device_operations mmapvtd_ops = { |
| 310 | .read_resources = mmapvtd_read_resources, |
| 311 | .set_resources = pci_dev_set_resources, |
| 312 | .enable_resources = pci_dev_enable_resources, |
| 313 | .init = mmapvtd_init, |
| 314 | .ops_pci = &soc_pci_ops, |
Marc Jones | 521a03f | 2020-10-19 13:46:59 -0600 | [diff] [blame] | 315 | #if CONFIG(HAVE_ACPI_TABLES) |
| 316 | .acpi_inject_dsdt = uncore_inject_dsdt, |
| 317 | #endif |
Jonathan Zhang | 8f89549 | 2020-01-16 11:16:45 -0800 | [diff] [blame] | 318 | }; |
| 319 | |
| 320 | static const unsigned short mmapvtd_ids[] = { |
| 321 | MMAP_VTD_CFG_REG_DEVID, /* Memory Map/IntelĀ® VT-d Configuration Registers */ |
| 322 | 0 |
| 323 | }; |
| 324 | |
| 325 | static const struct pci_driver mmapvtd_driver __pci_driver = { |
| 326 | .ops = &mmapvtd_ops, |
| 327 | .vendor = PCI_VENDOR_ID_INTEL, |
| 328 | .devices = mmapvtd_ids |
| 329 | }; |
Arthur Heymans | 77509be | 2020-10-22 17:11:22 +0200 | [diff] [blame] | 330 | |
| 331 | static void vtd_read_resources(struct device *dev) |
| 332 | { |
| 333 | pci_dev_read_resources(dev); |
| 334 | |
| 335 | configure_dpr(dev); |
| 336 | } |
| 337 | |
| 338 | static struct device_operations vtd_ops = { |
| 339 | .read_resources = vtd_read_resources, |
| 340 | .set_resources = pci_dev_set_resources, |
| 341 | .enable_resources = pci_dev_enable_resources, |
| 342 | .ops_pci = &soc_pci_ops, |
| 343 | }; |
| 344 | |
| 345 | /* VTD devices on other stacks */ |
| 346 | static const struct pci_driver vtd_driver __pci_driver = { |
| 347 | .ops = &vtd_ops, |
| 348 | .vendor = PCI_VENDOR_ID_INTEL, |
| 349 | .device = MMAP_VTD_STACK_CFG_REG_DEVID, |
| 350 | }; |
Arthur Heymans | 42a6f7e | 2020-11-10 16:46:18 +0100 | [diff] [blame] | 351 | |
| 352 | static void dmi3_init(struct device *dev) |
| 353 | { |
Arthur Heymans | 9d8a455 | 2021-02-02 19:21:24 +0100 | [diff] [blame] | 354 | if (CONFIG(INTEL_TXT) && skip_intel_txt_lockdown()) |
| 355 | return; |
Arthur Heymans | 42a6f7e | 2020-11-10 16:46:18 +0100 | [diff] [blame] | 356 | /* Disable error injection */ |
| 357 | pci_or_config16(dev, ERRINJCON, 1 << 0); |
| 358 | |
| 359 | /* |
| 360 | * DMIRCBAR registers are not TXT lockable, but the BAR enable |
| 361 | * bit is. TXT requires that DMIRCBAR be disabled for security. |
| 362 | */ |
| 363 | pci_and_config32(dev, DMIRCBAR, ~(1 << 0)); |
| 364 | } |
| 365 | |
| 366 | static struct device_operations dmi3_ops = { |
| 367 | .read_resources = pci_dev_read_resources, |
| 368 | .set_resources = pci_dev_set_resources, |
| 369 | .enable_resources = pci_dev_enable_resources, |
| 370 | .init = dmi3_init, |
| 371 | .ops_pci = &soc_pci_ops, |
| 372 | }; |
| 373 | |
| 374 | static const struct pci_driver dmi3_driver __pci_driver = { |
| 375 | .ops = &dmi3_ops, |
| 376 | .vendor = PCI_VENDOR_ID_INTEL, |
| 377 | .device = DMI3_DEVID, |
| 378 | }; |
Arthur Heymans | 7a36ca5 | 2020-11-10 15:55:31 +0100 | [diff] [blame] | 379 | |
| 380 | static void iio_dfx_global_init(struct device *dev) |
| 381 | { |
Arthur Heymans | 9d8a455 | 2021-02-02 19:21:24 +0100 | [diff] [blame] | 382 | if (CONFIG(INTEL_TXT) && skip_intel_txt_lockdown()) |
| 383 | return; |
| 384 | |
Arthur Heymans | 7a36ca5 | 2020-11-10 15:55:31 +0100 | [diff] [blame] | 385 | uint16_t reg16; |
| 386 | pci_or_config16(dev, IIO_DFX_LCK_CTL, 0x3ff); |
| 387 | reg16 = pci_read_config16(dev, IIO_DFX_TSWCTL0); |
| 388 | reg16 &= ~(1 << 4); // allow ib mmio cfg |
| 389 | reg16 &= ~(1 << 5); // ignore acs p2p ma lpbk |
| 390 | reg16 |= (1 << 3); // me disable |
| 391 | pci_write_config16(dev, IIO_DFX_TSWCTL0, reg16); |
| 392 | } |
| 393 | |
| 394 | static const unsigned short iio_dfx_global_ids[] = { |
| 395 | 0x202d, |
| 396 | 0x203d, |
| 397 | 0 |
| 398 | }; |
| 399 | |
| 400 | static struct device_operations iio_dfx_global_ops = { |
| 401 | .read_resources = pci_dev_read_resources, |
| 402 | .set_resources = pci_dev_set_resources, |
| 403 | .enable_resources = pci_dev_enable_resources, |
| 404 | .init = iio_dfx_global_init, |
| 405 | .ops_pci = &soc_pci_ops, |
| 406 | }; |
| 407 | |
| 408 | static const struct pci_driver iio_dfx_global_driver __pci_driver = { |
| 409 | .ops = &iio_dfx_global_ops, |
| 410 | .vendor = PCI_VENDOR_ID_INTEL, |
| 411 | .devices = iio_dfx_global_ids, |
| 412 | }; |