Angel Pons | c3f58f6 | 2020-04-05 15:46:41 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 2 | |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 3 | #include <soc/iomap.h> |
| 4 | #include <soc/irq.h> |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 5 | |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 6 | Scope(\) |
| 7 | { |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 8 | /* IO-Trap at 0x800. This is the ACPI->SMI communication interface. */ |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 9 | |
| 10 | OperationRegion(IO_T, SystemIO, 0x800, 0x10) |
| 11 | Field(IO_T, ByteAcc, NoLock, Preserve) |
| 12 | { |
| 13 | Offset(0x8), |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 14 | TRP0, 8 /* IO-Trap at 0x808 */ |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 15 | } |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 16 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 17 | /* Intel Legacy Block */ |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 18 | OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE) |
| 19 | Field (ILBS, AnyAcc, NoLock, Preserve) |
| 20 | { |
| 21 | Offset (0x8), |
| 22 | PRTA, 8, |
| 23 | PRTB, 8, |
| 24 | PRTC, 8, |
| 25 | PRTD, 8, |
| 26 | PRTE, 8, |
| 27 | PRTF, 8, |
| 28 | PRTG, 8, |
| 29 | PRTH, 8, |
| 30 | } |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 31 | } |
Duncan Laurie | 7fbe20b | 2013-11-04 17:00:22 -0800 | [diff] [blame] | 32 | |
Kyösti Mälkki | d06f800 | 2021-01-27 20:25:51 +0200 | [diff] [blame] | 33 | External (\TOLM, IntObj) |
| 34 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 35 | Name(_HID,EISAID("PNP0A08")) /* PCIe */ |
| 36 | Name(_CID,EISAID("PNP0A03")) /* PCI */ |
Duncan Laurie | 053bd07 | 2013-11-04 17:19:16 -0800 | [diff] [blame] | 37 | |
Duncan Laurie | 053bd07 | 2013-11-04 17:19:16 -0800 | [diff] [blame] | 38 | Name(_BBN, 0) |
| 39 | |
Martin Roth | 6149233 | 2015-11-23 10:38:10 -0700 | [diff] [blame] | 40 | Name (MCRS, ResourceTemplate() |
| 41 | { |
Matt DeVillier | 21a9bf8 | 2020-12-18 19:33:46 -0600 | [diff] [blame] | 42 | /* Bus Numbers */ |
Martin Roth | 6149233 | 2015-11-23 10:38:10 -0700 | [diff] [blame] | 43 | WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, |
| 44 | 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) |
| 45 | |
Matt DeVillier | 21a9bf8 | 2020-12-18 19:33:46 -0600 | [diff] [blame] | 46 | /* IO Region 0 */ |
Martin Roth | 6149233 | 2015-11-23 10:38:10 -0700 | [diff] [blame] | 47 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 48 | 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) |
| 49 | |
Matt DeVillier | 21a9bf8 | 2020-12-18 19:33:46 -0600 | [diff] [blame] | 50 | /* PCI Config Space */ |
Martin Roth | 6149233 | 2015-11-23 10:38:10 -0700 | [diff] [blame] | 51 | Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) |
| 52 | |
Matt DeVillier | 21a9bf8 | 2020-12-18 19:33:46 -0600 | [diff] [blame] | 53 | /* IO Region 1 */ |
Martin Roth | 6149233 | 2015-11-23 10:38:10 -0700 | [diff] [blame] | 54 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 55 | 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) |
| 56 | |
Matt DeVillier | 21a9bf8 | 2020-12-18 19:33:46 -0600 | [diff] [blame] | 57 | /* VGA memory (0xa0000-0xbffff) */ |
Martin Roth | 6149233 | 2015-11-23 10:38:10 -0700 | [diff] [blame] | 58 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 59 | Cacheable, ReadWrite, |
| 60 | 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, |
| 61 | 0x00020000,,, ASEG) |
| 62 | |
Matt DeVillier | 21a9bf8 | 2020-12-18 19:33:46 -0600 | [diff] [blame] | 63 | /* OPROM reserved (0xc0000-0xc3fff) */ |
Martin Roth | 6149233 | 2015-11-23 10:38:10 -0700 | [diff] [blame] | 64 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 65 | Cacheable, ReadWrite, |
| 66 | 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, |
| 67 | 0x00004000,,, OPR0) |
| 68 | |
Matt DeVillier | 21a9bf8 | 2020-12-18 19:33:46 -0600 | [diff] [blame] | 69 | /* OPROM reserved (0xc4000-0xc7fff) */ |
Martin Roth | 6149233 | 2015-11-23 10:38:10 -0700 | [diff] [blame] | 70 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 71 | Cacheable, ReadWrite, |
| 72 | 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, |
| 73 | 0x00004000,,, OPR1) |
| 74 | |
Matt DeVillier | 21a9bf8 | 2020-12-18 19:33:46 -0600 | [diff] [blame] | 75 | /* OPROM reserved (0xc8000-0xcbfff) */ |
Martin Roth | 6149233 | 2015-11-23 10:38:10 -0700 | [diff] [blame] | 76 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 77 | Cacheable, ReadWrite, |
| 78 | 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, |
| 79 | 0x00004000,,, OPR2) |
| 80 | |
Matt DeVillier | 21a9bf8 | 2020-12-18 19:33:46 -0600 | [diff] [blame] | 81 | /* OPROM reserved (0xcc000-0xcffff) */ |
Martin Roth | 6149233 | 2015-11-23 10:38:10 -0700 | [diff] [blame] | 82 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 83 | Cacheable, ReadWrite, |
| 84 | 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, |
| 85 | 0x00004000,,, OPR3) |
| 86 | |
Matt DeVillier | 21a9bf8 | 2020-12-18 19:33:46 -0600 | [diff] [blame] | 87 | /* OPROM reserved (0xd0000-0xd3fff) */ |
Martin Roth | 6149233 | 2015-11-23 10:38:10 -0700 | [diff] [blame] | 88 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 89 | Cacheable, ReadWrite, |
| 90 | 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, |
| 91 | 0x00004000,,, OPR4) |
| 92 | |
Matt DeVillier | 21a9bf8 | 2020-12-18 19:33:46 -0600 | [diff] [blame] | 93 | /* OPROM reserved (0xd4000-0xd7fff) */ |
Martin Roth | 6149233 | 2015-11-23 10:38:10 -0700 | [diff] [blame] | 94 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 95 | Cacheable, ReadWrite, |
| 96 | 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, |
| 97 | 0x00004000,,, OPR5) |
| 98 | |
Matt DeVillier | 21a9bf8 | 2020-12-18 19:33:46 -0600 | [diff] [blame] | 99 | /* OPROM reserved (0xd8000-0xdbfff) */ |
Martin Roth | 6149233 | 2015-11-23 10:38:10 -0700 | [diff] [blame] | 100 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 101 | Cacheable, ReadWrite, |
| 102 | 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, |
| 103 | 0x00004000,,, OPR6) |
| 104 | |
Matt DeVillier | 21a9bf8 | 2020-12-18 19:33:46 -0600 | [diff] [blame] | 105 | /* OPROM reserved (0xdc000-0xdffff) */ |
Martin Roth | 6149233 | 2015-11-23 10:38:10 -0700 | [diff] [blame] | 106 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 107 | Cacheable, ReadWrite, |
| 108 | 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, |
| 109 | 0x00004000,,, OPR7) |
| 110 | |
Matt DeVillier | 21a9bf8 | 2020-12-18 19:33:46 -0600 | [diff] [blame] | 111 | /* BIOS Extension (0xe0000-0xe3fff) */ |
Martin Roth | 6149233 | 2015-11-23 10:38:10 -0700 | [diff] [blame] | 112 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 113 | Cacheable, ReadWrite, |
| 114 | 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, |
| 115 | 0x00004000,,, ESG0) |
| 116 | |
Matt DeVillier | 21a9bf8 | 2020-12-18 19:33:46 -0600 | [diff] [blame] | 117 | /* BIOS Extension (0xe4000-0xe7fff) */ |
Martin Roth | 6149233 | 2015-11-23 10:38:10 -0700 | [diff] [blame] | 118 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 119 | Cacheable, ReadWrite, |
| 120 | 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, |
| 121 | 0x00004000,,, ESG1) |
| 122 | |
Matt DeVillier | 21a9bf8 | 2020-12-18 19:33:46 -0600 | [diff] [blame] | 123 | /* BIOS Extension (0xe8000-0xebfff) */ |
Martin Roth | 6149233 | 2015-11-23 10:38:10 -0700 | [diff] [blame] | 124 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 125 | Cacheable, ReadWrite, |
| 126 | 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, |
| 127 | 0x00004000,,, ESG2) |
| 128 | |
Matt DeVillier | 21a9bf8 | 2020-12-18 19:33:46 -0600 | [diff] [blame] | 129 | /* BIOS Extension (0xec000-0xeffff) */ |
Martin Roth | 6149233 | 2015-11-23 10:38:10 -0700 | [diff] [blame] | 130 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 131 | Cacheable, ReadWrite, |
| 132 | 0x00000000, 0x000ec000, 0x000effff, 0x00000000, |
| 133 | 0x00004000,,, ESG3) |
| 134 | |
Matt DeVillier | 21a9bf8 | 2020-12-18 19:33:46 -0600 | [diff] [blame] | 135 | /* System BIOS (0xf0000-0xfffff) */ |
Martin Roth | 6149233 | 2015-11-23 10:38:10 -0700 | [diff] [blame] | 136 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 137 | Cacheable, ReadWrite, |
| 138 | 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, |
| 139 | 0x00010000,,, FSEG) |
| 140 | |
Matt DeVillier | 21a9bf8 | 2020-12-18 19:33:46 -0600 | [diff] [blame] | 141 | /* LPEA Memory Region (0x20000000-0x201FFFFF) */ |
Martin Roth | 6149233 | 2015-11-23 10:38:10 -0700 | [diff] [blame] | 142 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 143 | Cacheable, ReadWrite, |
| 144 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
Matt DeVillier | 6a7b707 | 2020-12-18 19:05:09 -0600 | [diff] [blame] | 145 | 0x00000000,,, LMEM) |
| 146 | |
Matt DeVillier | 21a9bf8 | 2020-12-18 19:33:46 -0600 | [diff] [blame] | 147 | /* PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) */ |
Kyösti Mälkki | 639cc9c | 2021-02-01 13:57:45 +0200 | [diff] [blame] | 148 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
Matt DeVillier | 6a7b707 | 2020-12-18 19:05:09 -0600 | [diff] [blame] | 149 | Cacheable, ReadWrite, |
| 150 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 151 | 0x00000000,,, PMEM) |
Martin Roth | 6149233 | 2015-11-23 10:38:10 -0700 | [diff] [blame] | 152 | |
Matt DeVillier | 21a9bf8 | 2020-12-18 19:33:46 -0600 | [diff] [blame] | 153 | /* TPM Area (0xfed40000-0xfed44fff) */ |
Martin Roth | 6149233 | 2015-11-23 10:38:10 -0700 | [diff] [blame] | 154 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 155 | Cacheable, ReadWrite, |
| 156 | 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, |
| 157 | 0x00005000,,, TPMR) |
| 158 | }) |
| 159 | |
Duncan Laurie | 053bd07 | 2013-11-04 17:19:16 -0800 | [diff] [blame] | 160 | Method (_CRS, 0, Serialized) |
| 161 | { |
Duncan Laurie | 053bd07 | 2013-11-04 17:19:16 -0800 | [diff] [blame] | 162 | |
Matt DeVillier | 6a7b707 | 2020-12-18 19:05:09 -0600 | [diff] [blame] | 163 | /* Update LPEA resource area */ |
| 164 | CreateDWordField (MCRS, ^LMEM._MIN, LMIN) |
| 165 | CreateDWordField (MCRS, ^LMEM._MAX, LMAX) |
| 166 | CreateDWordField (MCRS, ^LMEM._LEN, LLEN) |
| 167 | If (LAnd (LNotEqual (LPFW, Zero), LEqual (LPEN, One))) |
| 168 | { |
| 169 | Store (LPFW, LMIN) |
| 170 | Store (0x00100000, LLEN) |
| 171 | Subtract (Add (LMIN, LLEN), One, LMAX) |
| 172 | } |
| 173 | Else |
| 174 | { |
| 175 | Store (Zero, LMIN) |
| 176 | Store (Zero, LMAX) |
| 177 | Store (Zero, LLEN) |
| 178 | } |
| 179 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 180 | /* Update PCI resource area */ |
Matt DeVillier | 6a7b707 | 2020-12-18 19:05:09 -0600 | [diff] [blame] | 181 | CreateDWordField (MCRS, ^PMEM._MIN, PMIN) |
| 182 | CreateDWordField (MCRS, ^PMEM._MAX, PMAX) |
| 183 | CreateDWordField (MCRS, ^PMEM._LEN, PLEN) |
Duncan Laurie | 053bd07 | 2013-11-04 17:19:16 -0800 | [diff] [blame] | 184 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 185 | /* TOLM is BMBOUND accessible from IOSF so is saved in NVS */ |
Duncan Laurie | 053bd07 | 2013-11-04 17:19:16 -0800 | [diff] [blame] | 186 | Store (\TOLM, PMIN) |
Dave Frodin | 2eaa0d4 | 2015-04-23 06:04:46 -0600 | [diff] [blame] | 187 | Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX) |
Duncan Laurie | 053bd07 | 2013-11-04 17:19:16 -0800 | [diff] [blame] | 188 | Add (Subtract (PMAX, PMIN), 1, PLEN) |
| 189 | |
| 190 | Return (MCRS) |
| 191 | } |
| 192 | |
Duncan Laurie | 7fbe20b | 2013-11-04 17:00:22 -0800 | [diff] [blame] | 193 | /* Device Resource Consumption */ |
| 194 | Device (PDRC) |
| 195 | { |
| 196 | Name (_HID, EISAID("PNP0C02")) |
| 197 | Name (_UID, 1) |
| 198 | |
| 199 | Name (PDRS, ResourceTemplate() { |
| 200 | Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE) |
Kyösti Mälkki | 6d08544 | 2021-02-14 01:55:18 +0200 | [diff] [blame] | 201 | Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) |
Duncan Laurie | 7fbe20b | 2013-11-04 17:00:22 -0800 | [diff] [blame] | 202 | Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE) |
Duncan Laurie | 7fbe20b | 2013-11-04 17:00:22 -0800 | [diff] [blame] | 203 | Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE) |
| 204 | Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE) |
| 205 | Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE) |
| 206 | Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE) |
| 207 | Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) |
Duncan Laurie | 7fbe20b | 2013-11-04 17:00:22 -0800 | [diff] [blame] | 208 | }) |
| 209 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 210 | /* Current Resource Settings */ |
Duncan Laurie | 7fbe20b | 2013-11-04 17:00:22 -0800 | [diff] [blame] | 211 | Method (_CRS, 0, Serialized) |
| 212 | { |
| 213 | Return(PDRS) |
| 214 | } |
| 215 | } |
Duncan Laurie | 93966e8 | 2013-11-04 17:28:19 -0800 | [diff] [blame] | 216 | |
| 217 | Method (_OSC, 4) |
| 218 | { |
| 219 | /* Check for proper GUID */ |
| 220 | If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) |
| 221 | { |
| 222 | /* Let OS control everything */ |
| 223 | Return (Arg3) |
| 224 | } |
| 225 | Else |
| 226 | { |
| 227 | /* Unrecognized UUID */ |
| 228 | CreateDWordField (Arg3, 0, CDW1) |
| 229 | Or (CDW1, 4, CDW1) |
| 230 | Return (Arg3) |
| 231 | } |
| 232 | } |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 233 | |
Duncan Laurie | 2e65796 | 2013-12-13 16:43:11 -0800 | [diff] [blame] | 234 | /* IOSF MBI Interface for kernel access */ |
| 235 | Device (IOSF) |
| 236 | { |
| 237 | Name (_HID, "INT33BD") |
| 238 | Name (_CID, "INT33BD") |
| 239 | Name (_UID, 1) |
| 240 | |
| 241 | Name (RBUF, ResourceTemplate () |
| 242 | { |
| 243 | /* MCR / MDR / MCRX */ |
| 244 | Memory32Fixed (ReadWrite, 0, 12, RBAR) |
| 245 | }) |
| 246 | |
| 247 | Method (_CRS) |
| 248 | { |
| 249 | CreateDwordField (^RBUF, ^RBAR._BAS, RBAS) |
Kyösti Mälkki | 6d08544 | 2021-02-14 01:55:18 +0200 | [diff] [blame] | 250 | Store (Add (CONFIG_MMCONF_BASE_ADDRESS, 0xD0), RBAS) |
Duncan Laurie | 2e65796 | 2013-12-13 16:43:11 -0800 | [diff] [blame] | 251 | Return (^RBUF) |
| 252 | } |
| 253 | } |
| 254 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 255 | /* LPC Bridge 0:1f.0 */ |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 256 | #include "lpc.asl" |
| 257 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 258 | /* USB XHCI 0:14.0 */ |
Duncan Laurie | 3f94a74 | 2014-01-14 14:59:28 -0800 | [diff] [blame] | 259 | #include "xhci.asl" |
| 260 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 261 | /* IRQ routing for each PCI device */ |
Aaron Durbin | 3bde3d7 | 2013-11-04 21:45:52 -0600 | [diff] [blame] | 262 | #include "irqroute.asl" |
Duncan Laurie | bb0d1ea | 2013-12-03 10:00:20 -0800 | [diff] [blame] | 263 | |
Matt DeVillier | 21a9bf8 | 2020-12-18 19:33:46 -0600 | [diff] [blame] | 264 | /* PCI Express Ports 0:1c.x */ |
Ted Kuo | 6ecaf65 | 2014-09-16 15:31:21 +0800 | [diff] [blame] | 265 | #include "pcie.asl" |
| 266 | |
Duncan Laurie | 430bf0d | 2013-12-10 14:37:42 -0800 | [diff] [blame] | 267 | Scope (\_SB) |
| 268 | { |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 269 | /* GPIO Devices */ |
Duncan Laurie | 430bf0d | 2013-12-10 14:37:42 -0800 | [diff] [blame] | 270 | #include "gpio.asl" |
Matt DeVillier | e34a770 | 2017-01-09 01:35:48 -0600 | [diff] [blame] | 271 | } |
Duncan Laurie | 430bf0d | 2013-12-10 14:37:42 -0800 | [diff] [blame] | 272 | |
Matt DeVillier | e34a770 | 2017-01-09 01:35:48 -0600 | [diff] [blame] | 273 | Scope (\_SB.PCI0) |
| 274 | { |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 275 | /* LPSS Devices */ |
Duncan Laurie | 430bf0d | 2013-12-10 14:37:42 -0800 | [diff] [blame] | 276 | #include "lpss.asl" |
| 277 | |
Angel Pons | 26b49cc | 2020-07-07 17:17:51 +0200 | [diff] [blame] | 278 | /* SCC Devices */ |
Duncan Laurie | 430bf0d | 2013-12-10 14:37:42 -0800 | [diff] [blame] | 279 | #include "scc.asl" |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 280 | |
Matt DeVillier | 21a9bf8 | 2020-12-18 19:33:46 -0600 | [diff] [blame] | 281 | /* LPE Device */ |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 282 | #include "lpe.asl" |
Duncan Laurie | 430bf0d | 2013-12-10 14:37:42 -0800 | [diff] [blame] | 283 | } |
Matt DeVillier | c6589ae | 2020-11-28 13:17:54 -0600 | [diff] [blame] | 284 | |
| 285 | /* Integrated graphics 0:2.0 */ |
| 286 | #include <drivers/intel/gma/acpi/gfx.asl> |