Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 2 | |
| 3 | Name(_HID,EISAID("PNP0A08")) // PCIe |
| 4 | Name(_CID,EISAID("PNP0A03")) // PCI |
| 5 | |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 6 | Name(_BBN, 0) |
| 7 | |
| 8 | Device (MCHC) |
| 9 | { |
| 10 | Name(_ADR, 0x00000000) // 0:0.0 |
| 11 | |
| 12 | OperationRegion(MCHP, PCI_Config, 0x00, 0x100) |
| 13 | Field (MCHP, DWordAcc, NoLock, Preserve) |
| 14 | { |
| 15 | Offset (0x40), // EPBAR |
| 16 | EPEN, 1, // Enable |
| 17 | , 11, // |
Patrick Rudolph | 2af2f2c | 2019-03-26 14:33:16 +0100 | [diff] [blame] | 18 | EPBR, 27, // EPBAR |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 19 | |
| 20 | Offset (0x48), // MCHBAR |
| 21 | MHEN, 1, // Enable |
Patrick Rudolph | 2af2f2c | 2019-03-26 14:33:16 +0100 | [diff] [blame] | 22 | , 14, // |
| 23 | MHBR, 24, // MCHBAR |
Patrick Rudolph | 0b643d2 | 2017-07-05 20:07:06 +0200 | [diff] [blame] | 24 | Offset (0x54), |
| 25 | DVEN, 32, |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 26 | Offset (0x60), // PCIe BAR |
| 27 | PXEN, 1, // Enable |
| 28 | PXSZ, 2, // BAR size |
| 29 | , 23, // |
Patrick Rudolph | 2af2f2c | 2019-03-26 14:33:16 +0100 | [diff] [blame] | 30 | PXBR, 13, // PCIe BAR |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 31 | |
| 32 | Offset (0x68), // DMIBAR |
| 33 | DMEN, 1, // Enable |
| 34 | , 11, // |
Patrick Rudolph | 2af2f2c | 2019-03-26 14:33:16 +0100 | [diff] [blame] | 35 | DMBR, 27, // DMIBAR |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 36 | |
| 37 | Offset (0x70), // ME Base Address |
| 38 | MEBA, 64, |
| 39 | |
| 40 | // ... |
| 41 | |
| 42 | Offset (0x80), // PAM0 |
| 43 | , 4, |
| 44 | PM0H, 2, |
| 45 | , 2, |
| 46 | Offset (0x81), // PAM1 |
| 47 | PM1L, 2, |
| 48 | , 2, |
| 49 | PM1H, 2, |
| 50 | , 2, |
| 51 | Offset (0x82), // PAM2 |
| 52 | PM2L, 2, |
| 53 | , 2, |
| 54 | PM2H, 2, |
| 55 | , 2, |
| 56 | Offset (0x83), // PAM3 |
| 57 | PM3L, 2, |
| 58 | , 2, |
| 59 | PM3H, 2, |
| 60 | , 2, |
| 61 | Offset (0x84), // PAM4 |
| 62 | PM4L, 2, |
| 63 | , 2, |
| 64 | PM4H, 2, |
| 65 | , 2, |
| 66 | Offset (0x85), // PAM5 |
| 67 | PM5L, 2, |
| 68 | , 2, |
| 69 | PM5H, 2, |
| 70 | , 2, |
| 71 | Offset (0x86), // PAM6 |
| 72 | PM6L, 2, |
| 73 | , 2, |
| 74 | PM6H, 2, |
| 75 | , 2, |
| 76 | |
| 77 | Offset (0xa0), // Top of Used Memory |
| 78 | TOM, 64, |
| 79 | |
| 80 | Offset (0xbc), // Top of Low Used Memory |
| 81 | TLUD, 32, |
| 82 | } |
| 83 | |
Duncan Laurie | 1b3207e | 2012-07-18 15:33:45 -0700 | [diff] [blame] | 84 | Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */ |
| 85 | Name (CTCC, 0) /* CTDP Current Selection */ |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 86 | Name (CTCN, 0) /* CTDP Nominal Select */ |
| 87 | Name (CTCD, 1) /* CTDP Down Select */ |
| 88 | Name (CTCU, 2) /* CTDP Up Select */ |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 89 | |
Patrick Rudolph | 2af2f2c | 2019-03-26 14:33:16 +0100 | [diff] [blame] | 90 | OperationRegion (MCHB, SystemMemory, \_SB.PCI0.MCHC.MHBR << 15, 0x8000) |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 91 | Field (MCHB, DWordAcc, Lock, Preserve) |
| 92 | { |
| 93 | Offset (0x5930), |
| 94 | CTDN, 15, /* CTDP Nominal PL1 */ |
| 95 | Offset (0x59a0), |
| 96 | PL1V, 15, /* Power Limit 1 Value */ |
| 97 | PL1E, 1, /* Power Limit 1 Enable */ |
| 98 | PL1C, 1, /* Power Limit 1 Clamp */ |
| 99 | PL1T, 7, /* Power Limit 1 Time */ |
| 100 | Offset (0x59a4), |
| 101 | PL2V, 15, /* Power Limit 2 Value */ |
| 102 | PL2E, 1, /* Power Limit 2 Enable */ |
| 103 | PL2C, 1, /* Power Limit 2 Clamp */ |
| 104 | PL2T, 7, /* Power Limit 2 Time */ |
| 105 | Offset (0x5f3c), |
| 106 | TARN, 8, /* CTDP Nominal Turbo Activation Ratio */ |
| 107 | Offset (0x5f40), |
| 108 | CTDD, 15, /* CTDP Down PL1 */ |
| 109 | , 1, |
| 110 | TARD, 8, /* CTDP Down Turbo Activation Ratio */ |
| 111 | Offset (0x5f48), |
| 112 | CTDU, 15, /* CTDP Up PL1 */ |
| 113 | , 1, |
| 114 | TARU, 8, /* CTDP Up Turbo Activation Ratio */ |
| 115 | Offset (0x5f50), |
| 116 | CTCS, 2, /* CTDP Select */ |
| 117 | Offset (0x5f54), |
| 118 | TARS, 8, /* Turbo Activation Ratio Select */ |
| 119 | } |
| 120 | |
| 121 | /* |
| 122 | * Search CPU0 _PSS looking for control=arg0 and then |
| 123 | * return previous P-state entry number for new _PPC |
| 124 | * |
| 125 | * Format of _PSS: |
| 126 | * Name (_PSS, Package () { |
| 127 | * Package (6) { freq, power, tlat, blat, control, status } |
| 128 | * } |
| 129 | */ |
Christian Walter | be3979c | 2019-12-18 15:07:59 +0100 | [diff] [blame] | 130 | External (\_SB.CP00._PSS) |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 131 | Method (PSSS, 1, NotSerialized) |
| 132 | { |
Furquan Shaikh | 9e94cce | 2020-06-01 13:44:57 -0700 | [diff] [blame] | 133 | Local0 = 1 /* Start at P1 */ |
| 134 | Local1 = SizeOf (\_SB.CP00._PSS) |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 135 | |
Furquan Shaikh | 9e94cce | 2020-06-01 13:44:57 -0700 | [diff] [blame] | 136 | While (Local0 < Local1) { |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 137 | /* Store _PSS entry Control value to Local2 */ |
Furquan Shaikh | 9e94cce | 2020-06-01 13:44:57 -0700 | [diff] [blame] | 138 | Local2 = DeRefOf (Index (DeRefOf (Index (\_SB.CP00._PSS, Local0)), 4)) >> 8 |
| 139 | If (Local2 == Arg0) { |
| 140 | Return (Local0 - 1) |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 141 | } |
Furquan Shaikh | 9e94cce | 2020-06-01 13:44:57 -0700 | [diff] [blame] | 142 | Local0++ |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 143 | } |
| 144 | |
| 145 | Return (0) |
| 146 | } |
| 147 | |
| 148 | /* Set TDP Down */ |
| 149 | Method (STND, 0, Serialized) |
| 150 | { |
Duncan Laurie | 1b3207e | 2012-07-18 15:33:45 -0700 | [diff] [blame] | 151 | If (Acquire (CTCM, 100)) { |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 152 | Return (0) |
| 153 | } |
Angel Pons | 5cd8c7c | 2020-08-03 19:26:45 +0200 | [diff] [blame] | 154 | If (CTCD == CTCC) { |
Duncan Laurie | 1b3207e | 2012-07-18 15:33:45 -0700 | [diff] [blame] | 155 | Release (CTCM) |
| 156 | Return (0) |
| 157 | } |
| 158 | |
Angel Pons | 5cd8c7c | 2020-08-03 19:26:45 +0200 | [diff] [blame] | 159 | Debug = "Set TDP Down" |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 160 | |
| 161 | /* Set CTC */ |
Furquan Shaikh | 9e94cce | 2020-06-01 13:44:57 -0700 | [diff] [blame] | 162 | CTCS = CTCD |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 163 | |
| 164 | /* Set TAR */ |
Furquan Shaikh | 9e94cce | 2020-06-01 13:44:57 -0700 | [diff] [blame] | 165 | TARS = TARD |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 166 | |
| 167 | /* Set PPC limit and notify OS */ |
Furquan Shaikh | 9e94cce | 2020-06-01 13:44:57 -0700 | [diff] [blame] | 168 | PPCM = PSSS (TARD) |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 169 | PPCN () |
| 170 | |
| 171 | /* Set PL2 to 1.25 * PL1 */ |
Furquan Shaikh | 9e94cce | 2020-06-01 13:44:57 -0700 | [diff] [blame] | 172 | PL2V = (CTDD * 125) / 100 |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 173 | |
| 174 | /* Set PL1 */ |
Furquan Shaikh | 9e94cce | 2020-06-01 13:44:57 -0700 | [diff] [blame] | 175 | PL1V = CTDD |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 176 | |
Duncan Laurie | 1b3207e | 2012-07-18 15:33:45 -0700 | [diff] [blame] | 177 | /* Store the new TDP Down setting */ |
Furquan Shaikh | 9e94cce | 2020-06-01 13:44:57 -0700 | [diff] [blame] | 178 | CTCC = CTCD |
Duncan Laurie | 1b3207e | 2012-07-18 15:33:45 -0700 | [diff] [blame] | 179 | |
| 180 | Release (CTCM) |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 181 | Return (1) |
| 182 | } |
| 183 | |
| 184 | /* Set TDP Nominal from Down */ |
| 185 | Method (STDN, 0, Serialized) |
| 186 | { |
Duncan Laurie | 1b3207e | 2012-07-18 15:33:45 -0700 | [diff] [blame] | 187 | If (Acquire (CTCM, 100)) { |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 188 | Return (0) |
| 189 | } |
Angel Pons | 5cd8c7c | 2020-08-03 19:26:45 +0200 | [diff] [blame] | 190 | If (CTCN == CTCC) { |
Duncan Laurie | 1b3207e | 2012-07-18 15:33:45 -0700 | [diff] [blame] | 191 | Release (CTCM) |
| 192 | Return (0) |
| 193 | } |
| 194 | |
Angel Pons | 5cd8c7c | 2020-08-03 19:26:45 +0200 | [diff] [blame] | 195 | Debug = "Set TDP Nominal" |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 196 | |
| 197 | /* Set PL1 */ |
Furquan Shaikh | 9e94cce | 2020-06-01 13:44:57 -0700 | [diff] [blame] | 198 | PL1V = CTDN |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 199 | |
| 200 | /* Set PL2 to 1.25 * PL1 */ |
Furquan Shaikh | 9e94cce | 2020-06-01 13:44:57 -0700 | [diff] [blame] | 201 | PL2V = (CTDN * 125) / 100 |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 202 | |
| 203 | /* Set PPC limit and notify OS */ |
Furquan Shaikh | 9e94cce | 2020-06-01 13:44:57 -0700 | [diff] [blame] | 204 | PPCM = PSSS (TARN) |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 205 | PPCN () |
| 206 | |
| 207 | /* Set TAR */ |
Furquan Shaikh | 9e94cce | 2020-06-01 13:44:57 -0700 | [diff] [blame] | 208 | TARS = TARN |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 209 | |
| 210 | /* Set CTC */ |
Furquan Shaikh | 9e94cce | 2020-06-01 13:44:57 -0700 | [diff] [blame] | 211 | CTCS = CTCN |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 212 | |
Duncan Laurie | 1b3207e | 2012-07-18 15:33:45 -0700 | [diff] [blame] | 213 | /* Store the new TDP Nominal setting */ |
Furquan Shaikh | 9e94cce | 2020-06-01 13:44:57 -0700 | [diff] [blame] | 214 | CTCC = CTCN |
Duncan Laurie | 1b3207e | 2012-07-18 15:33:45 -0700 | [diff] [blame] | 215 | |
| 216 | Release (CTCM) |
Duncan Laurie | 55864ef | 2012-07-16 12:27:42 -0700 | [diff] [blame] | 217 | Return (1) |
| 218 | } |
| 219 | } |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 220 | |
| 221 | // Current Resource Settings |
Martin Roth | fc70643 | 2015-08-18 16:56:05 -0600 | [diff] [blame] | 222 | Name (MCRS, ResourceTemplate() |
| 223 | { |
| 224 | // Bus Numbers |
| 225 | WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, |
| 226 | 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) |
| 227 | |
| 228 | // IO Region 0 |
| 229 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 230 | 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) |
| 231 | |
| 232 | // PCI Config Space |
| 233 | Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) |
| 234 | |
| 235 | // IO Region 1 |
| 236 | DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, |
| 237 | 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) |
| 238 | |
| 239 | // VGA memory (0xa0000-0xbffff) |
| 240 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 241 | Cacheable, ReadWrite, |
| 242 | 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, |
| 243 | 0x00020000,,, ASEG) |
| 244 | |
| 245 | // OPROM reserved (0xc0000-0xc3fff) |
| 246 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 247 | Cacheable, ReadWrite, |
| 248 | 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, |
| 249 | 0x00004000,,, OPR0) |
| 250 | |
| 251 | // OPROM reserved (0xc4000-0xc7fff) |
| 252 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 253 | Cacheable, ReadWrite, |
| 254 | 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, |
| 255 | 0x00004000,,, OPR1) |
| 256 | |
| 257 | // OPROM reserved (0xc8000-0xcbfff) |
| 258 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 259 | Cacheable, ReadWrite, |
| 260 | 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, |
| 261 | 0x00004000,,, OPR2) |
| 262 | |
| 263 | // OPROM reserved (0xcc000-0xcffff) |
| 264 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 265 | Cacheable, ReadWrite, |
| 266 | 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, |
| 267 | 0x00004000,,, OPR3) |
| 268 | |
| 269 | // OPROM reserved (0xd0000-0xd3fff) |
| 270 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 271 | Cacheable, ReadWrite, |
| 272 | 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, |
| 273 | 0x00004000,,, OPR4) |
| 274 | |
| 275 | // OPROM reserved (0xd4000-0xd7fff) |
| 276 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 277 | Cacheable, ReadWrite, |
| 278 | 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, |
| 279 | 0x00004000,,, OPR5) |
| 280 | |
| 281 | // OPROM reserved (0xd8000-0xdbfff) |
| 282 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 283 | Cacheable, ReadWrite, |
| 284 | 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, |
| 285 | 0x00004000,,, OPR6) |
| 286 | |
| 287 | // OPROM reserved (0xdc000-0xdffff) |
| 288 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 289 | Cacheable, ReadWrite, |
| 290 | 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, |
| 291 | 0x00004000,,, OPR7) |
| 292 | |
| 293 | // BIOS Extension (0xe0000-0xe3fff) |
| 294 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 295 | Cacheable, ReadWrite, |
| 296 | 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, |
| 297 | 0x00004000,,, ESG0) |
| 298 | |
| 299 | // BIOS Extension (0xe4000-0xe7fff) |
| 300 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 301 | Cacheable, ReadWrite, |
| 302 | 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, |
| 303 | 0x00004000,,, ESG1) |
| 304 | |
| 305 | // BIOS Extension (0xe8000-0xebfff) |
| 306 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 307 | Cacheable, ReadWrite, |
| 308 | 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, |
| 309 | 0x00004000,,, ESG2) |
| 310 | |
| 311 | // BIOS Extension (0xec000-0xeffff) |
| 312 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 313 | Cacheable, ReadWrite, |
| 314 | 0x00000000, 0x000ec000, 0x000effff, 0x00000000, |
| 315 | 0x00004000,,, ESG3) |
| 316 | |
| 317 | // System BIOS (0xf0000-0xfffff) |
| 318 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 319 | Cacheable, ReadWrite, |
| 320 | 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, |
| 321 | 0x00010000,,, FSEG) |
| 322 | |
| 323 | // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) |
| 324 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 325 | Cacheable, ReadWrite, |
| 326 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 327 | 0x00000000,,, PM01) |
| 328 | |
| 329 | // TPM Area (0xfed40000-0xfed44fff) |
| 330 | DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, |
| 331 | Cacheable, ReadWrite, |
| 332 | 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, |
| 333 | 0x00005000,,, TPMR) |
| 334 | }) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 335 | |
| 336 | Method (_CRS, 0, Serialized) |
| 337 | { |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 338 | // Find PCI resource area in MCRS |
Martin Roth | fc70643 | 2015-08-18 16:56:05 -0600 | [diff] [blame] | 339 | CreateDwordField(MCRS, ^PM01._MIN, PMIN) |
| 340 | CreateDwordField(MCRS, ^PM01._MAX, PMAX) |
| 341 | CreateDwordField(MCRS, ^PM01._LEN, PLEN) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 342 | |
| 343 | // Fix up PCI memory region |
| 344 | // Start with Top of Lower Usable DRAM |
Furquan Shaikh | 4b4c0c6 | 2020-06-01 13:47:28 -0700 | [diff] [blame] | 345 | // Lower 20 bits of TOLUD register need to be masked since they contain lock and |
| 346 | // reserved bits. |
| 347 | Local0 = ^MCHC.TLUD & (0xfff << 20) |
Furquan Shaikh | 9e94cce | 2020-06-01 13:44:57 -0700 | [diff] [blame] | 348 | Local1 = ^MCHC.MEBA |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 349 | |
| 350 | // Check if ME base is equal |
Furquan Shaikh | 9e94cce | 2020-06-01 13:44:57 -0700 | [diff] [blame] | 351 | If (Local0 == Local1) { |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 352 | // Use Top Of Memory instead |
Furquan Shaikh | 4b4c0c6 | 2020-06-01 13:47:28 -0700 | [diff] [blame] | 353 | // Lower 20 bits of TOM register need to be masked since they contain lock and |
| 354 | // reserved bits. |
| 355 | Local0 = ^MCHC.TOM & (0x7ffff << 20) |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 356 | } |
| 357 | |
Furquan Shaikh | 9e94cce | 2020-06-01 13:44:57 -0700 | [diff] [blame] | 358 | PMIN = Local0 |
| 359 | PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1 |
| 360 | PLEN = PMAX - PMIN + 1 |
Stefan Reinauer | 00636b0 | 2012-04-04 00:08:51 +0200 | [diff] [blame] | 361 | |
| 362 | Return (MCRS) |
| 363 | } |