Arthur Heymans | f1b1412 | 2023-07-14 20:44:55 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <stdint.h> |
| 4 | |
| 5 | /* |
| 6 | * GENOA MPIO mapping |
| 7 | * P0 -> [0-15] |
| 8 | * G0 -> [16-31] |
| 9 | * P1 -> [32-47] |
| 10 | * G1 -> [48-63] |
| 11 | * P2 -> [64-79] |
| 12 | * G2 -> [80-95] |
| 13 | * P3 -> [96-111] |
| 14 | * G3 -> [112-127] |
| 15 | * P4 -> [128-131] |
| 16 | * P5 -> [132-136] |
| 17 | */ |
| 18 | |
| 19 | enum mpio_type { |
| 20 | PCIE, |
| 21 | SATA, |
| 22 | }; |
| 23 | |
| 24 | /* Sync with PCIE_HOTPLUG_TYPE */ |
| 25 | enum mpio_hotplug { |
| 26 | HotplugDisabled, ///< Hotplug disable |
| 27 | Basic, ///< Basic Hotplug |
| 28 | ServerExpress, ///< Server Hotplug Express Module |
| 29 | Enhanced, ///< Enhanced |
| 30 | Inboard, ///< Inboard |
| 31 | ServerEntSSD, ///< Server Hotplug Enterprise SSD |
| 32 | UBM, ///< UBM Backplane |
| 33 | OCP, ///< OCP NIC 3.0 |
| 34 | }; |
| 35 | |
| 36 | enum pcie_link_speed { |
| 37 | MaxSupported, |
| 38 | Gen1, |
| 39 | Gen2, |
| 40 | Gen3, |
| 41 | Gen4, |
| 42 | Gen5, |
| 43 | }; |
| 44 | |
| 45 | /* Sync with PCIE_ASPM_TYPE */ |
Felix Held | 4e3d2a1 | 2024-02-22 16:40:07 +0100 | [diff] [blame^] | 46 | enum pcie_aspm { |
Arthur Heymans | f1b1412 | 2023-07-14 20:44:55 +0200 | [diff] [blame] | 47 | aspm_disabled, |
| 48 | L0s, |
| 49 | L1, |
| 50 | L0sL1, |
| 51 | }; |
| 52 | |
| 53 | struct vendorcode_amd_opensil_genoa_poc_mpio_config { |
| 54 | enum mpio_type type; |
| 55 | uint8_t start_lane; |
| 56 | uint8_t end_lane; |
| 57 | uint8_t gpio_group; |
| 58 | enum mpio_hotplug hotplug; |
| 59 | enum pcie_link_speed speed; |
Felix Held | 4e3d2a1 | 2024-02-22 16:40:07 +0100 | [diff] [blame^] | 60 | enum pcie_aspm aspm; |
Arthur Heymans | f1b1412 | 2023-07-14 20:44:55 +0200 | [diff] [blame] | 61 | uint8_t aspm_l1_1 : 1; |
| 62 | uint8_t aspm_l1_2 : 1; |
| 63 | uint8_t clock_pm : 1; |
| 64 | uint8_t bmc : 1; |
| 65 | }; |