Gabe Black | d40be11 | 2013-10-09 23:45:07 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2013 Google Inc. |
| 5 | * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 19 | */ |
| 20 | |
| 21 | #include <arch/io.h> |
| 22 | #include <console/console.h> |
| 23 | #include <soc/addressmap.h> |
| 24 | |
| 25 | #include "pmc.h" |
| 26 | #include "power.h" |
| 27 | |
| 28 | static struct tegra_pmc_regs * const pmc = (void *)TEGRA_PMC_BASE; |
| 29 | |
| 30 | static int partition_powered(int id) |
| 31 | { |
| 32 | return read32(&pmc->pwrgate_status) & (0x1 << id); |
| 33 | } |
| 34 | |
| 35 | static void power_ungate_partition(uint32_t id) |
| 36 | { |
| 37 | printk(BIOS_INFO, "Ungating power partition %d.\n", id); |
| 38 | |
| 39 | if (!partition_powered(id)) { |
| 40 | uint32_t pwrgate_toggle = read32(&pmc->pwrgate_toggle); |
| 41 | pwrgate_toggle &= ~(PMC_PWRGATE_TOGGLE_PARTID_MASK); |
| 42 | pwrgate_toggle |= (id << PMC_PWRGATE_TOGGLE_PARTID_SHIFT); |
| 43 | pwrgate_toggle |= PMC_PWRGATE_TOGGLE_START; |
| 44 | write32(pwrgate_toggle, &pmc->pwrgate_toggle); |
| 45 | |
| 46 | // Wait for the request to be accepted. |
| 47 | while (read32(&pmc->pwrgate_toggle) & PMC_PWRGATE_TOGGLE_START) |
| 48 | ; |
| 49 | printk(BIOS_DEBUG, "Power gate toggle request accepted.\n"); |
| 50 | |
| 51 | // Wait for the partition to be powered. |
| 52 | while (!partition_powered(id)) |
| 53 | ; |
| 54 | } |
| 55 | |
| 56 | printk(BIOS_INFO, "Ungated power partition %d.\n", id); |
| 57 | } |
| 58 | |
| 59 | void power_enable_cpu_rail(void) |
| 60 | { |
| 61 | // Set the power gate timer multiplier to 8 (why 8?). |
| 62 | uint32_t pwrgate_timer_mult = read32(&pmc->pwrgate_timer_mult); |
| 63 | pwrgate_timer_mult |= (0x3 << 0); |
| 64 | |
| 65 | /* |
| 66 | * From U-Boot: |
| 67 | * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz), |
| 68 | * set it for 5ms as per SysEng (102MHz/5mS = 510000). |
| 69 | */ |
| 70 | write32(510000, &pmc->cpupwrgood_timer); |
| 71 | |
| 72 | power_ungate_partition(POWER_PARTID_CRAIL); |
| 73 | |
| 74 | uint32_t cntrl = read32(&pmc->cntrl); |
| 75 | cntrl &= ~PMC_CNTRL_CPUPWRREQ_POLARITY; |
| 76 | cntrl |= PMC_CNTRL_CPUPWRREQ_OE; |
| 77 | write32(cntrl, &pmc->cntrl); |
| 78 | } |
| 79 | |
| 80 | void power_ungate_cpu(void) |
| 81 | { |
| 82 | // Ungate power to the non-core parts of the fast cluster. |
| 83 | power_ungate_partition(POWER_PARTID_C0NC); |
| 84 | |
| 85 | // Ungate power to CPU0 in the fast cluster. |
| 86 | power_ungate_partition(POWER_PARTID_CE0); |
| 87 | } |
Gabe Black | 4dc3e28 | 2014-05-06 15:33:37 -0700 | [diff] [blame^] | 88 | |
| 89 | int power_reset_status(void) |
| 90 | { |
| 91 | return read32(&pmc->rst_status) & 0x7; |
| 92 | } |