Stefan Reinauer | 9d5e36e | 2015-04-27 13:40:16 -0700 | [diff] [blame] | 1 | # TODO These two options look too similar |
Kyösti Mälkki | 5c3f384 | 2014-05-08 15:27:15 +0300 | [diff] [blame] | 2 | config PARALLEL_CPU_INIT |
Sven Schnelle | a2701c6 | 2012-07-29 17:42:52 +0200 | [diff] [blame] | 3 | bool |
Kyösti Mälkki | 5c3f384 | 2014-05-08 15:27:15 +0300 | [diff] [blame] | 4 | default n |
Sven Schnelle | a2701c6 | 2012-07-29 17:42:52 +0200 | [diff] [blame] | 5 | |
Stefan Reinauer | 9d5e36e | 2015-04-27 13:40:16 -0700 | [diff] [blame] | 6 | config PARALLEL_MP |
| 7 | def_bool n |
| 8 | help |
| 9 | This option uses common MP infrastructure for bringing up APs |
| 10 | in parallel. It additionally provides a more flexible mechanism |
| 11 | for sequencing the steps of bringing up the APs. |
| 12 | |
Aaron Durbin | b21e362 | 2016-12-07 00:32:19 -0600 | [diff] [blame] | 13 | config PARALLEL_MP_AP_WORK |
| 14 | def_bool n |
| 15 | depends on PARALLEL_MP |
| 16 | help |
| 17 | Allow APs to do other work after initialization instead of going |
| 18 | to sleep. |
Stefan Reinauer | 9d5e36e | 2015-04-27 13:40:16 -0700 | [diff] [blame] | 19 | |
Patrick Georgi | 0e9a925 | 2009-10-06 20:48:07 +0000 | [diff] [blame] | 20 | config UDELAY_LAPIC |
| 21 | bool |
| 22 | default n |
| 23 | |
Aaron Durbin | fd8291c | 2013-04-29 17:18:49 -0500 | [diff] [blame] | 24 | config LAPIC_MONOTONIC_TIMER |
| 25 | def_bool n |
| 26 | depends on UDELAY_LAPIC |
| 27 | select HAVE_MONOTONIC_TIMER |
| 28 | help |
Elyes HAOUAS | d6e9686 | 2016-08-21 10:12:15 +0200 | [diff] [blame] | 29 | Expose monotonic time using the local APIC. |
Aaron Durbin | fd8291c | 2013-04-29 17:18:49 -0500 | [diff] [blame] | 30 | |
Patrick Georgi | e135ac5 | 2012-11-20 11:53:47 +0100 | [diff] [blame] | 31 | config UDELAY_LAPIC_FIXED_FSB |
| 32 | int |
| 33 | |
Ronald G. Minnich | 669c4a9 | 2009-08-29 03:00:51 +0000 | [diff] [blame] | 34 | config UDELAY_TSC |
| 35 | bool |
| 36 | default n |
| 37 | |
Aaron Durbin | 8e73b5d | 2013-05-01 15:27:09 -0500 | [diff] [blame] | 38 | config TSC_CONSTANT_RATE |
| 39 | def_bool n |
| 40 | depends on UDELAY_TSC |
| 41 | help |
| 42 | This option asserts that the TSC ticks at a known constant rate. |
| 43 | Therefore, no TSC calibration is required. |
| 44 | |
Aaron Durbin | e850164 | 2013-04-29 22:22:55 -0500 | [diff] [blame] | 45 | config TSC_MONOTONIC_TIMER |
| 46 | def_bool n |
| 47 | depends on UDELAY_TSC |
| 48 | select HAVE_MONOTONIC_TIMER |
| 49 | help |
| 50 | Expose monotonic time using the TSC. |
| 51 | |
Stefan Reinauer | 0db6820 | 2012-08-07 14:44:51 -0700 | [diff] [blame] | 52 | config TSC_SYNC_LFENCE |
| 53 | bool |
| 54 | default n |
| 55 | help |
| 56 | The CPU driver should select this if the CPU needs |
| 57 | to execute an lfence instruction in order to synchronize |
| 58 | rdtsc. This is true for all modern AMD CPUs. |
| 59 | |
| 60 | config TSC_SYNC_MFENCE |
| 61 | bool |
| 62 | default n |
| 63 | help |
| 64 | The CPU driver should select this if the CPU needs |
| 65 | to execute an mfence instruction in order to synchronize |
| 66 | rdtsc. This is true for all modern Intel CPUs. |
| 67 | |
Aaron Durbin | ef10529 | 2016-05-05 10:34:22 -0500 | [diff] [blame] | 68 | config NO_FIXED_XIP_ROM_SIZE |
| 69 | bool |
| 70 | default n |
| 71 | help |
| 72 | The XIP_ROM_SIZE Kconfig variable is used globally on x86 |
| 73 | with the assumption that all chipsets utilize this value. |
| 74 | For the chipsets which do not use the variable it can lead |
| 75 | to unnecessary alignment constraints in cbfs for romstage. |
| 76 | Therefore, allow those chipsets a path to not be burdened. |
| 77 | |
Uwe Hermann | f9d4c2b | 2009-08-25 12:19:28 +0000 | [diff] [blame] | 78 | config XIP_ROM_SIZE |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 79 | hex |
Aaron Durbin | ef10529 | 2016-05-05 10:34:22 -0500 | [diff] [blame] | 80 | depends on !NO_FIXED_XIP_ROM_SIZE |
Patrick Georgi | f1ce6f2 | 2010-04-12 09:50:53 +0000 | [diff] [blame] | 81 | default 0x10000 |
Stefan Reinauer | 8aedcbc | 2010-12-16 23:37:17 +0000 | [diff] [blame] | 82 | |
| 83 | config CPU_ADDR_BITS |
| 84 | int |
| 85 | default 36 |
| 86 | |
| 87 | config LOGICAL_CPUS |
| 88 | bool |
| 89 | default y |
| 90 | |
Duncan Laurie | 8bb7723 | 2012-01-09 22:11:25 -0800 | [diff] [blame] | 91 | config SMM_TSEG |
| 92 | bool |
| 93 | default n |
Aaron Durbin | 50a3464 | 2013-01-03 17:38:47 -0600 | [diff] [blame] | 94 | |
| 95 | config SMM_MODULE_HEAP_SIZE |
| 96 | hex |
| 97 | default 0x4000 |
Vladimir Serbinenko | 44cbe10 | 2015-05-28 21:09:31 +0200 | [diff] [blame] | 98 | depends on SMM_TSEG |
Aaron Durbin | 50a3464 | 2013-01-03 17:38:47 -0600 | [diff] [blame] | 99 | help |
| 100 | This option determines the size of the heap within the SMM handler |
| 101 | modules. |
Aaron Durbin | 57686f8 | 2013-03-20 15:50:59 -0500 | [diff] [blame] | 102 | |
Raul E Rangel | d3b8393 | 2018-06-12 10:43:09 -0600 | [diff] [blame] | 103 | config SMM_MODULE_STACK_SIZE |
| 104 | hex |
| 105 | default 0x400 |
| 106 | depends on SMM_TSEG |
| 107 | help |
| 108 | This option determines the size of the stack within the SMM handler |
| 109 | modules. |
| 110 | |
Marshall Dawson | 46fc6847 | 2018-10-25 13:01:55 -0600 | [diff] [blame] | 111 | config SMM_STUB_STACK_SIZE |
| 112 | hex |
| 113 | default 0x400 |
| 114 | depends on SMM_TSEG |
| 115 | help |
| 116 | This option determines the size of the stack within the SMM handler |
| 117 | modules. |
| 118 | |
Patrick Georgi | ce2564a | 2015-09-05 20:21:24 +0200 | [diff] [blame] | 119 | config SMM_LAPIC_REMAP_MITIGATION |
| 120 | bool |
| 121 | default y if NORTHBRIDGE_INTEL_I945 |
| 122 | default y if NORTHBRIDGE_INTEL_GM45 |
| 123 | default y if NORTHBRIDGE_INTEL_NEHALEM |
| 124 | default n |
| 125 | |
Damien Zammit | 149c4c5 | 2015-11-28 21:27:05 +1100 | [diff] [blame] | 126 | config SERIALIZED_SMM_INITIALIZATION |
| 127 | bool |
| 128 | default n |
| 129 | help |
| 130 | On some CPUs, there is a race condition in SMM. |
| 131 | This can occur when both hyperthreads change SMM state |
| 132 | variables in parallel without coordination. |
| 133 | Setting this option serializes the SMM initialization |
| 134 | to avoid an ugly hang in the boot process at the cost |
| 135 | of a slightly longer boot time. |
| 136 | |
Aaron Durbin | 57686f8 | 2013-03-20 15:50:59 -0500 | [diff] [blame] | 137 | config X86_AMD_FIXED_MTRRS |
| 138 | bool |
| 139 | default n |
| 140 | help |
| 141 | This option informs the MTRR code to use the RdMem and WrMem fields |
| 142 | in the fixed MTRR MSRs. |
Aaron Durbin | e0785c0 | 2013-10-21 12:15:29 -0500 | [diff] [blame] | 143 | |
Aaron Durbin | c34713d | 2014-02-25 20:36:56 -0600 | [diff] [blame] | 144 | config MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING |
| 145 | def_bool n |
| 146 | help |
| 147 | On certain platforms a boot speed gain can be realized if mirroring |
| 148 | the payload data stored in non-volatile storage. On x86 systems the |
| 149 | payload would typically live in a memory-mapped SPI part. Copying |
Daniele Forsi | 53847a2 | 2014-07-22 18:00:56 +0200 | [diff] [blame] | 150 | the SPI contents to RAM before performing the load can speed up |
Aaron Durbin | c34713d | 2014-02-25 20:36:56 -0600 | [diff] [blame] | 151 | the boot process. |
David Hendricks | be6f8cb | 2014-03-21 17:09:29 -0700 | [diff] [blame] | 152 | |
Lee Leahy | ae738ac | 2016-07-24 08:03:37 -0700 | [diff] [blame] | 153 | config SOC_SETS_MSRS |
| 154 | bool |
| 155 | default n |
| 156 | help |
| 157 | The SoC requires different access methods for reading and writing |
| 158 | the MSRs. Use SoC specific routines to handle the MSR access. |