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Stefan Reinauer9d5e36e2015-04-27 13:40:16 -07001# TODO These two options look too similar
Kyösti Mälkki5c3f3842014-05-08 15:27:15 +03002config PARALLEL_CPU_INIT
Sven Schnellea2701c62012-07-29 17:42:52 +02003 bool
Kyösti Mälkki5c3f3842014-05-08 15:27:15 +03004 default n
Sven Schnellea2701c62012-07-29 17:42:52 +02005
Stefan Reinauer9d5e36e2015-04-27 13:40:16 -07006config PARALLEL_MP
7 def_bool n
8 help
9 This option uses common MP infrastructure for bringing up APs
10 in parallel. It additionally provides a more flexible mechanism
11 for sequencing the steps of bringing up the APs.
12
Aaron Durbinb21e3622016-12-07 00:32:19 -060013config PARALLEL_MP_AP_WORK
14 def_bool n
15 depends on PARALLEL_MP
16 help
17 Allow APs to do other work after initialization instead of going
18 to sleep.
Stefan Reinauer9d5e36e2015-04-27 13:40:16 -070019
Patrick Georgi0e9a9252009-10-06 20:48:07 +000020config UDELAY_LAPIC
21 bool
22 default n
23
Aaron Durbinfd8291c2013-04-29 17:18:49 -050024config LAPIC_MONOTONIC_TIMER
25 def_bool n
26 depends on UDELAY_LAPIC
27 select HAVE_MONOTONIC_TIMER
28 help
Elyes HAOUASd6e96862016-08-21 10:12:15 +020029 Expose monotonic time using the local APIC.
Aaron Durbinfd8291c2013-04-29 17:18:49 -050030
Patrick Georgie135ac52012-11-20 11:53:47 +010031config UDELAY_LAPIC_FIXED_FSB
32 int
33
Ronald G. Minnich669c4a92009-08-29 03:00:51 +000034config UDELAY_TSC
35 bool
36 default n
37
Aaron Durbin8e73b5d2013-05-01 15:27:09 -050038config TSC_CONSTANT_RATE
39 def_bool n
40 depends on UDELAY_TSC
41 help
42 This option asserts that the TSC ticks at a known constant rate.
43 Therefore, no TSC calibration is required.
44
Aaron Durbine8501642013-04-29 22:22:55 -050045config TSC_MONOTONIC_TIMER
46 def_bool n
47 depends on UDELAY_TSC
48 select HAVE_MONOTONIC_TIMER
49 help
50 Expose monotonic time using the TSC.
51
Stefan Reinauer0db68202012-08-07 14:44:51 -070052config TSC_SYNC_LFENCE
53 bool
54 default n
55 help
56 The CPU driver should select this if the CPU needs
57 to execute an lfence instruction in order to synchronize
58 rdtsc. This is true for all modern AMD CPUs.
59
60config TSC_SYNC_MFENCE
61 bool
62 default n
63 help
64 The CPU driver should select this if the CPU needs
65 to execute an mfence instruction in order to synchronize
66 rdtsc. This is true for all modern Intel CPUs.
67
Aaron Durbinef105292016-05-05 10:34:22 -050068config NO_FIXED_XIP_ROM_SIZE
69 bool
70 default n
71 help
72 The XIP_ROM_SIZE Kconfig variable is used globally on x86
73 with the assumption that all chipsets utilize this value.
74 For the chipsets which do not use the variable it can lead
75 to unnecessary alignment constraints in cbfs for romstage.
76 Therefore, allow those chipsets a path to not be burdened.
77
Uwe Hermannf9d4c2b2009-08-25 12:19:28 +000078config XIP_ROM_SIZE
Patrick Georgi0588d192009-08-12 15:00:51 +000079 hex
Aaron Durbinef105292016-05-05 10:34:22 -050080 depends on !NO_FIXED_XIP_ROM_SIZE
Patrick Georgif1ce6f22010-04-12 09:50:53 +000081 default 0x10000
Stefan Reinauer8aedcbc2010-12-16 23:37:17 +000082
83config CPU_ADDR_BITS
84 int
85 default 36
86
87config LOGICAL_CPUS
88 bool
89 default y
90
Duncan Laurie8bb77232012-01-09 22:11:25 -080091config SMM_TSEG
92 bool
93 default n
Aaron Durbin50a34642013-01-03 17:38:47 -060094
95config SMM_MODULE_HEAP_SIZE
96 hex
97 default 0x4000
Vladimir Serbinenko44cbe102015-05-28 21:09:31 +020098 depends on SMM_TSEG
Aaron Durbin50a34642013-01-03 17:38:47 -060099 help
100 This option determines the size of the heap within the SMM handler
101 modules.
Aaron Durbin57686f82013-03-20 15:50:59 -0500102
Raul E Rangeld3b83932018-06-12 10:43:09 -0600103config SMM_MODULE_STACK_SIZE
104 hex
105 default 0x400
106 depends on SMM_TSEG
107 help
108 This option determines the size of the stack within the SMM handler
109 modules.
110
Marshall Dawson46fc68472018-10-25 13:01:55 -0600111config SMM_STUB_STACK_SIZE
112 hex
113 default 0x400
114 depends on SMM_TSEG
115 help
116 This option determines the size of the stack within the SMM handler
117 modules.
118
Patrick Georgice2564a2015-09-05 20:21:24 +0200119config SMM_LAPIC_REMAP_MITIGATION
120 bool
121 default y if NORTHBRIDGE_INTEL_I945
122 default y if NORTHBRIDGE_INTEL_GM45
123 default y if NORTHBRIDGE_INTEL_NEHALEM
124 default n
125
Damien Zammit149c4c52015-11-28 21:27:05 +1100126config SERIALIZED_SMM_INITIALIZATION
127 bool
128 default n
129 help
130 On some CPUs, there is a race condition in SMM.
131 This can occur when both hyperthreads change SMM state
132 variables in parallel without coordination.
133 Setting this option serializes the SMM initialization
134 to avoid an ugly hang in the boot process at the cost
135 of a slightly longer boot time.
136
Aaron Durbin57686f82013-03-20 15:50:59 -0500137config X86_AMD_FIXED_MTRRS
138 bool
139 default n
140 help
141 This option informs the MTRR code to use the RdMem and WrMem fields
142 in the fixed MTRR MSRs.
Aaron Durbine0785c02013-10-21 12:15:29 -0500143
Aaron Durbinc34713d2014-02-25 20:36:56 -0600144config MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING
145 def_bool n
146 help
147 On certain platforms a boot speed gain can be realized if mirroring
148 the payload data stored in non-volatile storage. On x86 systems the
149 payload would typically live in a memory-mapped SPI part. Copying
Daniele Forsi53847a22014-07-22 18:00:56 +0200150 the SPI contents to RAM before performing the load can speed up
Aaron Durbinc34713d2014-02-25 20:36:56 -0600151 the boot process.
David Hendricksbe6f8cb2014-03-21 17:09:29 -0700152
Lee Leahyae738ac2016-07-24 08:03:37 -0700153config SOC_SETS_MSRS
154 bool
155 default n
156 help
157 The SoC requires different access methods for reading and writing
158 the MSRs. Use SoC specific routines to handle the MSR access.