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review.coreboot.org / coreboot / 4ce52f622ed7fbac4bf5545fd7d39256203cdefe / . / src / soc / amd / common / block / psp / Kconfig
blob: fc9769f6dcabddd4782463e3f5551f77812c627f [file] [log] [blame]
Marshall Dawson68243a52017-06-15 16:59:20 -0600[diff] [blame]1config SOC_AMD_COMMON_BLOCK_PSP
2 bool
Marshall Dawson68243a52017-06-15 16:59:20 -0600[diff] [blame]3 help
4 This option builds in the Platform Security Processor initialization
Marshall Dawsond6b72362020-03-05 11:44:24 -0700[diff] [blame]5 functions. Do not select this directly in SoC code, select
6 SOC_AMD_COMMON_BLOCK_PSP_GENx instead.
7
8config SOC_AMD_COMMON_BLOCK_PSP_GEN1
9 bool
Marshall Dawsond6b72362020-03-05 11:44:24 -0700[diff] [blame]10 select SOC_AMD_COMMON_BLOCK_PSP
Felix Held0c70b4a2020-04-13 22:38:13 +0200[diff] [blame]11 help
Felix Heldb6ef2972020-11-06 00:27:23 +0100[diff] [blame]12 Used by the PSP in AMD systems before family 17h, e.g. stoneyridge.
Marshall Dawsond6b72362020-03-05 11:44:24 -0700[diff] [blame]13
14config SOC_AMD_COMMON_BLOCK_PSP_GEN2
15 bool
Marshall Dawsond6b72362020-03-05 11:44:24 -0700[diff] [blame]16 select SOC_AMD_COMMON_BLOCK_PSP
Felix Held198cc262022-04-29 19:25:19 +0200[diff] [blame]17 select SOC_AMD_COMMON_BLOCK_SMN
Felix Held0c70b4a2020-04-13 22:38:13 +0200[diff] [blame]18 help
Felix Heldb6ef2972020-11-06 00:27:23 +0100[diff] [blame]19 Used by the PSP in AMD family 17h, 19h and possibly newer CPUs.
Marshall Dawson596ecec2017-10-12 16:04:08 -0600[diff] [blame]20
21config SOC_AMD_PSP_SELECTABLE_SMU_FW
22 bool
Marshall Dawson596ecec2017-10-12 16:04:08 -0600[diff] [blame]23 help
24 Some PSP implementations allow storing SMU firmware into cbfs and
25 calling the PSP to load the blobs at the proper time.
26
27 The soc/<codename> should select this if its PSP supports the feature
28 and each mainboard can choose to select an appropriate fanless or
29 fanned set of blobs. Ask your AMD representative whether your APU
30 is considered fanless.
Fred Reitberger1e25fd42022-02-02 13:30:18 -0500[diff] [blame]31
Felix Held51d1f302023-10-04 21:10:36 +0200[diff] [blame]32config SOC_AMD_COMMON_BLOCK_PSP_SPL
Jason Gleneskfd539b42022-01-28 14:53:07 -0800[diff] [blame]33 bool
Jason Gleneskfd539b42022-01-28 14:53:07 -0800[diff] [blame]34 help
Felix Held51d1f302023-10-04 21:10:36 +0200[diff] [blame]35 Select this option in the SoC's Kconfig to include the Security Patch
36 Level (SPL) support code. This code will only send the actual SPL
37 fuse update command to the PSP if the PERFORM_SPL_FUSING option is
38 also selected.
39
40config PERFORM_SPL_FUSING
41 bool "Send SPL fusing command to PSP"
42 default n
43 depends on SOC_AMD_COMMON_BLOCK_PSP_SPL
44 help
45 Send the Security Patch Level (SPL) fusing command to the PSP in
46 order to update the minimum SPL version to be written to the SoC's
47 fuse bits. This will prevent using any embedded firmware components
48 with lower SPL version.
49
50 If unsure, answer 'n'
51
52config SPL_TABLE_FILE
53 string "SPL table file override"
54 depends on SOC_AMD_COMMON_BLOCK_PSP_SPL
55 help
56 Provide a mainboard-specific Security Patch Level (SPL) table file
57 override. The SPL file is required to support PSP FW anti-rollback
58 and needs to be created by AMD. The default SPL file specified in the
59 SoC's fw.cfg is in the corresponding folder of the amd_blobs submodule
60 and applies to all boards that use the SoC without verstage on PSP.
61 In the verstage on PSP case, a different SPL file is specific as an
62 override via this Kconfig option.
63
64config HAVE_SPL_RW_AB_FILE
65 bool "Have a separate mainboard-specific SPL file in RW A/B partitions"
66 default n
67 depends on SOC_AMD_COMMON_BLOCK_PSP_SPL
68 depends on VBOOT_SLOTS_RW_AB
69 help
70 Have separate mainboard-specific Security Patch Level (SPL) table
71 file for the RW A/B FMAP partitions.
72
73config SPL_RW_AB_TABLE_FILE
74 string "Separate SPL table file override for RW A/B partitions"
75 depends on HAVE_SPL_RW_AB_FILE
Ritul Guru8da38042022-01-10 18:44:24 +0530[diff] [blame]76
77config PSP_PLATFORM_SECURE_BOOT
78 bool "Platform secure boot enable"
79 depends on SOC_AMD_COMMON_BLOCK_PSP_GEN2
80 default n
81 help
82 Select this config to enable PSP Platform Secure Boot.
83
84 Platform Secure Boot will automatically be fused on boot if the
85 coreboot ROM is properly signed and can not be disabled once fused.
86 Refer AMD PSB user guide doc# 56654, Revision# 1.00, this document is
87 only available with NDA customers.
Karthikeyan Ramasubramanian8420ccc2022-12-22 12:01:01 -0700[diff] [blame]88
89config PSP_INCLUDES_HSP
90 bool
91 depends on SOC_AMD_COMMON_BLOCK_PSP
92 default n
93 help
94 Select this config to indicate SoC includes Hardware Security Processor(HSP).
Zheng Bao6bc06982023-02-14 13:26:31 +0800[diff] [blame]95
96config AMD_FWM_POSITION_20000_DEFAULT
Martin Roth9a9e9a12023-10-30 14:56:41 -0600[diff] [blame]97 bool
Zheng Bao6bc06982023-02-14 13:26:31 +0800[diff] [blame]98
99config AMD_FWM_POSITION_420000_DEFAULT
Martin Roth9a9e9a12023-10-30 14:56:41 -0600[diff] [blame]100 bool
Zheng Bao6bc06982023-02-14 13:26:31 +0800[diff] [blame]101
102config AMD_FWM_POSITION_820000_DEFAULT
Martin Roth9a9e9a12023-10-30 14:56:41 -0600[diff] [blame]103 bool
Zheng Bao6bc06982023-02-14 13:26:31 +0800[diff] [blame]104
105config AMD_FWM_POSITION_C20000_DEFAULT
Martin Roth9a9e9a12023-10-30 14:56:41 -0600[diff] [blame]106 bool
Zheng Bao6bc06982023-02-14 13:26:31 +0800[diff] [blame]107
108config AMD_FWM_POSITION_E20000_DEFAULT
Martin Roth9a9e9a12023-10-30 14:56:41 -0600[diff] [blame]109 bool
Zheng Bao6bc06982023-02-14 13:26:31 +0800[diff] [blame]110
111config AMD_FWM_POSITION_F20000_DEFAULT
Martin Roth9a9e9a12023-10-30 14:56:41 -0600[diff] [blame]112 bool
Zheng Bao6bc06982023-02-14 13:26:31 +0800[diff] [blame]113
114config AMD_FWM_POSITION_FA0000_DEFAULT
Martin Roth9a9e9a12023-10-30 14:56:41 -0600[diff] [blame]115 bool
Zheng Bao6bc06982023-02-14 13:26:31 +0800[diff] [blame]116
Martin Roth4ce52f62023-11-07 13:35:44 -0700[diff] [blame^]117choice
Zheng Bao6bc06982023-02-14 13:26:31 +0800[diff] [blame]118 prompt "AMD FW position"
119 default AMD_FWM_POSITION_420000 if AMD_FWM_POSITION_420000_DEFAULT
120 default AMD_FWM_POSITION_820000 if AMD_FWM_POSITION_820000_DEFAULT
121 default AMD_FWM_POSITION_C20000 if AMD_FWM_POSITION_C20000_DEFAULT
122 default AMD_FWM_POSITION_E20000 if AMD_FWM_POSITION_E20000_DEFAULT
123 default AMD_FWM_POSITION_F20000 if AMD_FWM_POSITION_F20000_DEFAULT
124 default AMD_FWM_POSITION_FA0000 if AMD_FWM_POSITION_FA0000_DEFAULT
125 default AMD_FWM_POSITION_20000
126 help
127 Set the position on flash offset where the AMD FW needs to be.
128 This position is relative to a 16MB flash window. If the flash
129 size is smaller than 16MB it gets mapped at the top of that window.
130
131config AMD_FWM_POSITION_20000
132 bool "0x20000"
133
134config AMD_FWM_POSITION_420000
135 bool "0x420000"
136
137config AMD_FWM_POSITION_820000
138 bool "0x820000"
139
140config AMD_FWM_POSITION_C20000
141 bool "0xC20000"
142
143config AMD_FWM_POSITION_E20000
144 bool "0xE20000"
145
146config AMD_FWM_POSITION_F20000
147 bool "0xF20000"
148
149config AMD_FWM_POSITION_FA0000
150 bool "0xFA0000"
151
152endchoice
153
154config AMD_FWM_POSITION
155 hex
156 default 0x20000 if AMD_FWM_POSITION_20000
157 default 0x420000 if AMD_FWM_POSITION_420000
158 default 0x820000 if AMD_FWM_POSITION_820000
159 default 0xc20000 if AMD_FWM_POSITION_C20000
160 default 0xe20000 if AMD_FWM_POSITION_E20000
161 default 0xf20000 if AMD_FWM_POSITION_F20000
162 default 0xfa0000 if AMD_FWM_POSITION_FA0000