Tan, Lean Sheng | 4ce4afa | 2020-08-25 18:07:16 -0700 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <arch/cpu.h> |
| 4 | #include <console/console.h> |
| 5 | #include <cpu/intel/microcode.h> |
| 6 | #include <cpu/x86/msr.h> |
| 7 | #include <cpu/x86/name.h> |
| 8 | #include <device/pci.h> |
| 9 | #include <device/pci_ids.h> |
| 10 | #include <device/pci_ops.h> |
| 11 | #include <intelblocks/mp_init.h> |
| 12 | #include <soc/bootblock.h> |
| 13 | #include <soc/pch.h> |
| 14 | #include <soc/pci_devs.h> |
| 15 | #include <string.h> |
| 16 | |
| 17 | /* |
| 18 | * TODO: Add EHL specific CPU/SA/PCH/IGD IDs here |
| 19 | */ |
| 20 | |
| 21 | static inline uint8_t get_dev_revision(pci_devfn_t dev) |
| 22 | { |
| 23 | return pci_read_config8(dev, PCI_REVISION_ID); |
| 24 | } |
| 25 | |
| 26 | static inline uint16_t get_dev_id(pci_devfn_t dev) |
| 27 | { |
| 28 | return pci_read_config16(dev, PCI_DEVICE_ID); |
| 29 | } |
| 30 | |
| 31 | static void report_cpu_info(void) |
| 32 | { |
| 33 | uint32_t i, cpu_id, cpu_feature_flag; |
| 34 | char cpu_name[49]; |
| 35 | int vt, txt, aes; |
| 36 | static const char *const mode[] = {"NOT ", ""}; |
| 37 | const char *cpu_type = "Unknown"; |
| 38 | |
| 39 | fill_processor_name(cpu_name); |
| 40 | cpu_id = cpu_get_cpuid(); |
| 41 | |
| 42 | /* Look for string to match the name */ |
| 43 | for (i = 0; i < ARRAY_SIZE(cpu_table); i++) { |
| 44 | if (cpu_table[i].cpuid == cpu_id) { |
| 45 | cpu_type = cpu_table[i].name; |
| 46 | break; |
| 47 | } |
| 48 | } |
| 49 | |
| 50 | printk(BIOS_DEBUG, "CPU: %s\n", cpu_name); |
| 51 | printk(BIOS_DEBUG, "CPU: ID %x, %s, ucode: %08x\n", |
| 52 | cpu_id, cpu_type, get_current_microcode_rev()); |
| 53 | |
| 54 | cpu_feature_flag = cpu_get_feature_flags_ecx(); |
| 55 | aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0; |
| 56 | txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0; |
| 57 | vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0; |
| 58 | printk(BIOS_DEBUG, |
| 59 | "CPU: AES %ssupported, TXT %ssupported, VT %ssupported\n", |
| 60 | mode[aes], mode[txt], mode[vt]); |
| 61 | } |
| 62 | |
| 63 | static void report_mch_info(void) |
| 64 | { |
| 65 | int i; |
| 66 | pci_devfn_t dev = SA_DEV_ROOT; |
| 67 | uint16_t mchid = get_dev_id(dev); |
| 68 | uint8_t mch_revision = get_dev_revision(dev); |
| 69 | const char *mch_type = "Unknown"; |
| 70 | |
| 71 | for (i = 0; i < ARRAY_SIZE(mch_table); i++) { |
| 72 | if (mch_table[i].mchid == mchid) { |
| 73 | mch_type = mch_table[i].name; |
| 74 | break; |
| 75 | } |
| 76 | } |
| 77 | |
| 78 | printk(BIOS_DEBUG, "MCH: device id %04x (rev %02x) is %s\n", |
| 79 | mchid, mch_revision, mch_type); |
| 80 | } |
| 81 | |
| 82 | static void report_pch_info(void) |
| 83 | { |
| 84 | int i; |
| 85 | pci_devfn_t dev = PCH_DEV_ESPI; |
| 86 | uint16_t espiid = get_dev_id(dev); |
| 87 | const char *pch_type = "Unknown"; |
| 88 | |
| 89 | for (i = 0; i < ARRAY_SIZE(pch_table); i++) { |
| 90 | if (pch_table[i].espiid == espiid) { |
| 91 | pch_type = pch_table[i].name; |
| 92 | break; |
| 93 | } |
| 94 | } |
| 95 | printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n", |
| 96 | espiid, get_dev_revision(dev), pch_type); |
| 97 | } |
| 98 | |
| 99 | static void report_igd_info(void) |
| 100 | { |
| 101 | int i; |
| 102 | pci_devfn_t dev = SA_DEV_IGD; |
| 103 | uint16_t igdid = get_dev_id(dev); |
| 104 | const char *igd_type = "Unknown"; |
| 105 | |
| 106 | for (i = 0; i < ARRAY_SIZE(igd_table); i++) { |
| 107 | if (igd_table[i].igdid == igdid) { |
| 108 | igd_type = igd_table[i].name; |
| 109 | break; |
| 110 | } |
| 111 | } |
| 112 | printk(BIOS_DEBUG, "IGD: device id %04x (rev %02x) is %s\n", |
| 113 | igdid, get_dev_revision(dev), igd_type); |
| 114 | } |
| 115 | |
| 116 | void report_platform_info(void) |
| 117 | { |
| 118 | report_cpu_info(); |
| 119 | report_mch_info(); |
| 120 | report_pch_info(); |
| 121 | report_igd_info(); |
| 122 | } |