Olivier Langlois | ccc7d1f | 2013-06-03 01:30:25 -0400 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of msrtool. |
| 3 | * |
| 4 | * Copyright (C) 2013 Olivier Langlois <olivier@olivierlanglois.net> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Olivier Langlois | ccc7d1f | 2013-06-03 01:30:25 -0400 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include "msrtool.h" |
| 17 | |
| 18 | int intel_atom_probe(const struct targetdef *target, const struct cpuid_t *id) { |
Lubomir Rintel | 199a23c | 2017-01-22 22:19:24 +0100 | [diff] [blame] | 19 | return ((VENDOR_INTEL == id->vendor) && |
| 20 | (0x6 == id->family) && |
| 21 | (0x1c == id->model)); |
Olivier Langlois | ccc7d1f | 2013-06-03 01:30:25 -0400 | [diff] [blame] | 22 | } |
| 23 | |
| 24 | const struct msrdef intel_atom_msrs[] = { |
| 25 | {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "Pentium Processor\ |
| 26 | Machine-Check Exception Address", { |
| 27 | { BITS_EOT } |
| 28 | }}, |
| 29 | {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "Pentium Processor\ |
| 30 | Machine-Check Exception Type", { |
| 31 | { BITS_EOT } |
| 32 | }}, |
| 33 | {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STEP_COUNTER", "TSC", { |
| 34 | { BITS_EOT } |
| 35 | }}, |
| 36 | {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", { |
| 37 | { BITS_EOT } |
| 38 | }}, |
| 39 | {0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBL_CR_POWERON", "", { |
| 40 | { BITS_EOT } |
| 41 | }}, |
| 42 | {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scaleable Bus Speed", { |
| 43 | { BITS_EOT } |
| 44 | }}, |
| 45 | {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { |
| 46 | { BITS_EOT } |
| 47 | }}, |
| 48 | {0x11e, MSRTYPE_RDWR, MSR2(0,0), "MSR_BBL_CR_CTL3", "", { |
| 49 | { BITS_EOT } |
| 50 | }}, |
| 51 | {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { |
| 52 | { 63, 19, RESERVED }, |
| 53 | { 44, 5, "Maximum Bus Ratio", "R/O", PRESENT_DEC, { |
| 54 | { BITVAL_EOT } |
| 55 | }}, |
| 56 | { 39, 24, RESERVED }, |
| 57 | { 15, 16, "Current Performance State Value", "R/O", PRESENT_HEX, { |
| 58 | { BITVAL_EOT } |
| 59 | }}, |
| 60 | { BITS_EOT } |
| 61 | }}, |
| 62 | {0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", { |
| 63 | { BITS_EOT } |
| 64 | }}, |
| 65 | {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE0", "", { |
| 66 | { BITS_EOT } |
| 67 | }}, |
| 68 | {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK0", "", { |
| 69 | { BITS_EOT } |
| 70 | }}, |
| 71 | {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE1", "", { |
| 72 | { BITS_EOT } |
| 73 | }}, |
| 74 | {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK1", "", { |
| 75 | { BITS_EOT } |
| 76 | }}, |
| 77 | {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE2", "", { |
| 78 | { BITS_EOT } |
| 79 | }}, |
| 80 | {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK2", "", { |
| 81 | { BITS_EOT } |
| 82 | }}, |
| 83 | {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE3", "", { |
| 84 | { BITS_EOT } |
| 85 | }}, |
| 86 | {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK3", "", { |
| 87 | { BITS_EOT } |
| 88 | }}, |
| 89 | {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE4", "", { |
| 90 | { BITS_EOT } |
| 91 | }}, |
| 92 | {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK4", "", { |
| 93 | { BITS_EOT } |
| 94 | }}, |
| 95 | {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE5", "", { |
| 96 | { BITS_EOT } |
| 97 | }}, |
| 98 | {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK5", "", { |
| 99 | { BITS_EOT } |
| 100 | }}, |
| 101 | {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE6", "", { |
| 102 | { BITS_EOT } |
| 103 | }}, |
| 104 | {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK6", "", { |
| 105 | { BITS_EOT } |
| 106 | }}, |
| 107 | #if 0 |
| 108 | {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE7", "", { |
| 109 | { BITS_EOT } |
| 110 | }}, |
| 111 | {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK7", "", { |
| 112 | { BITS_EOT } |
| 113 | }}, |
| 114 | #endif |
| 115 | {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { |
| 116 | { BITS_EOT } |
| 117 | }}, |
| 118 | {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { |
| 119 | { BITS_EOT } |
| 120 | }}, |
| 121 | {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { |
| 122 | { BITS_EOT } |
| 123 | }}, |
| 124 | {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { |
| 125 | { BITS_EOT } |
| 126 | }}, |
| 127 | {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { |
| 128 | { BITS_EOT } |
| 129 | }}, |
| 130 | {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { |
| 131 | { BITS_EOT } |
| 132 | }}, |
| 133 | {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { |
| 134 | { BITS_EOT } |
| 135 | }}, |
| 136 | {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { |
| 137 | { BITS_EOT } |
| 138 | }}, |
| 139 | {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { |
| 140 | { BITS_EOT } |
| 141 | }}, |
| 142 | {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { |
| 143 | { BITS_EOT } |
| 144 | }}, |
| 145 | {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { |
| 146 | { BITS_EOT } |
| 147 | }}, |
| 148 | /* if CPUID.01H: ECX[15] = 1 */ |
| 149 | {0x345, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", { |
| 150 | /* Additional info available at Section 17.4.1 of |
| 151 | * Intel 64 and IA-32 Architecures Software Developer's |
| 152 | * Manual, Volume 3. |
| 153 | */ |
| 154 | { 63, 50, RESERVED }, |
| 155 | { 13, 1, "Counter width", "R/O", PRESENT_BIN, { |
| 156 | { MSR1(0), "Nothing" }, |
| 157 | { MSR1(1), "Full width of counter writable via IA32_A_PMCx" }, |
| 158 | { BITVAL_EOT } |
| 159 | }}, |
| 160 | { 12, 1, "SMM_FREEZE", "R/O", PRESENT_BIN, { |
| 161 | { MSR1(0), "Nothing" }, |
| 162 | { MSR1(1), "Freeze while SMM is supported" }, |
| 163 | { BITVAL_EOT } |
| 164 | }}, |
| 165 | { 11, 4, "PEBS_REC_FORMAT", "R/O", PRESENT_HEX, { |
| 166 | { BITVAL_EOT } |
| 167 | }}, |
| 168 | { 7, 1, "PEBSSaveArchRegs", "R/O", PRESENT_BIN, { |
| 169 | { BITVAL_EOT } |
| 170 | }}, |
| 171 | { 6, 1, "PEBS Record Format", "R/O", PRESENT_BIN, { |
| 172 | { BITVAL_EOT } |
| 173 | }}, |
| 174 | { 5, 6, "LBR Format", "R/O", PRESENT_HEX, { |
| 175 | { BITVAL_EOT } |
| 176 | }}, |
| 177 | { BITS_EOT } |
| 178 | }}, |
Kyösti Mälkki | 8b72aaf | 2018-05-13 09:19:00 +0300 | [diff] [blame] | 179 | {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", { |
Olivier Langlois | ccc7d1f | 2013-06-03 01:30:25 -0400 | [diff] [blame] | 180 | { BITS_EOT } |
| 181 | }}, |
Kyösti Mälkki | 8b72aaf | 2018-05-13 09:19:00 +0300 | [diff] [blame] | 182 | {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", { |
Olivier Langlois | ccc7d1f | 2013-06-03 01:30:25 -0400 | [diff] [blame] | 183 | { BITS_EOT } |
| 184 | }}, |
Kyösti Mälkki | 8b72aaf | 2018-05-13 09:19:00 +0300 | [diff] [blame] | 185 | {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", { |
Olivier Langlois | ccc7d1f | 2013-06-03 01:30:25 -0400 | [diff] [blame] | 186 | { BITS_EOT } |
| 187 | }}, |
| 188 | {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", { |
| 189 | { BITS_EOT } |
| 190 | }}, |
| 191 | {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", { |
| 192 | { BITS_EOT } |
| 193 | }}, |
| 194 | {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", { |
| 195 | { BITS_EOT } |
| 196 | }}, |
| 197 | {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", { |
| 198 | { BITS_EOT } |
| 199 | }}, |
| 200 | {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", { |
| 201 | { BITS_EOT } |
| 202 | }}, |
Kyösti Mälkki | 15a971b | 2018-05-14 09:09:29 +0300 | [diff] [blame] | 203 | {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { |
Olivier Langlois | ccc7d1f | 2013-06-03 01:30:25 -0400 | [diff] [blame] | 204 | { BITS_EOT } |
| 205 | }}, |
Kyösti Mälkki | 15a971b | 2018-05-14 09:09:29 +0300 | [diff] [blame] | 206 | {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { |
Olivier Langlois | ccc7d1f | 2013-06-03 01:30:25 -0400 | [diff] [blame] | 207 | { BITS_EOT } |
| 208 | }}, |
Kyösti Mälkki | 15a971b | 2018-05-14 09:09:29 +0300 | [diff] [blame] | 209 | {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { |
Olivier Langlois | ccc7d1f | 2013-06-03 01:30:25 -0400 | [diff] [blame] | 210 | { BITS_EOT } |
| 211 | }}, |
Kyösti Mälkki | 15a971b | 2018-05-14 09:09:29 +0300 | [diff] [blame] | 212 | {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { |
Olivier Langlois | ccc7d1f | 2013-06-03 01:30:25 -0400 | [diff] [blame] | 213 | { BITS_EOT } |
| 214 | }}, |
Kyösti Mälkki | 15a971b | 2018-05-14 09:09:29 +0300 | [diff] [blame] | 215 | {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { |
Olivier Langlois | ccc7d1f | 2013-06-03 01:30:25 -0400 | [diff] [blame] | 216 | { BITS_EOT } |
| 217 | }}, |
Kyösti Mälkki | 15a971b | 2018-05-14 09:09:29 +0300 | [diff] [blame] | 218 | {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { |
Olivier Langlois | ccc7d1f | 2013-06-03 01:30:25 -0400 | [diff] [blame] | 219 | { BITS_EOT } |
| 220 | }}, |
| 221 | |
| 222 | /* ========================================================================== |
| 223 | * Per core MSRs |
| 224 | * ========================================================================== |
| 225 | */ |
| 226 | |
| 227 | {0x6, MSRTYPE_RDWR, MSR2(0,0), "IA32_MONITOR_FILTER_SIZE", "", { |
| 228 | { BITS_EOT } |
| 229 | }}, |
| 230 | {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STEP_COUNTER", "TSC", { |
| 231 | { BITS_EOT } |
| 232 | }}, |
| 233 | {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "APIC BASE", { |
| 234 | /* In Intel's manual there is MAXPHYWID, |
| 235 | * which determine index of highest bit of |
| 236 | * APIC Base itself, so marking it as |
| 237 | * 'RESERVED'. |
| 238 | */ |
| 239 | { 63, 52, RESERVED }, |
| 240 | { 11, 1, "APIC Global Enable", "R/W", PRESENT_BIN, { |
| 241 | { BITVAL_EOT } |
| 242 | }}, |
| 243 | { 10, 1, "x2APIC mode", "R/W", PRESENT_BIN, { |
| 244 | { MSR1(0), "x2APIC mode is disabled" }, |
| 245 | { MSR1(1), "x2APIC mode is enabled" }, |
| 246 | { BITVAL_EOT } |
| 247 | }}, |
| 248 | { 9, 1, RESERVED }, |
| 249 | { 8, 1, "BSP Flag", "R/W", PRESENT_BIN, { |
| 250 | { BITVAL_EOT } |
| 251 | }}, |
| 252 | { 7, 8, RESERVED }, |
| 253 | { BITS_EOT } |
| 254 | }}, |
| 255 | /* if CPUID.01H: ECX[bit 5 or bit 6] = 1 */ |
| 256 | {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", |
| 257 | "Control features in Intel 64Processor", { |
| 258 | { 63, 48, RESERVED }, |
| 259 | /* if CPUID.01H: ECX[6] = 1 */ |
| 260 | { 15, 1, "SENTER Global Enable", "R/WL", PRESENT_BIN, { |
| 261 | { MSR1(0), "SENTER leaf functions are disabled" }, |
| 262 | { MSR1(1), "SENTER leaf functions are enabled" }, |
| 263 | { BITVAL_EOT } |
| 264 | }}, |
| 265 | /* if CPUID.01H: ECX[6] = 1 */ |
| 266 | { 14, 7, "SENTER Local Function Enables", "R/WL", PRESENT_BIN, { |
| 267 | { BITVAL_EOT } |
| 268 | }}, |
| 269 | { 7, 5, RESERVED }, |
| 270 | /* if CPUID.01H: ECX[5 or 6] = 1 */ |
| 271 | { 2, 1, "VMX outside of SMX operation", "R/WL", PRESENT_BIN, { |
| 272 | /* This bit enables VMX for system executive |
| 273 | * that do not require SMX. |
| 274 | */ |
| 275 | { MSR1(0), "VMX outside of SMX operation disabled" }, |
| 276 | { MSR1(1), "VMX outside of SMX operation enabled" }, |
| 277 | { BITVAL_EOT } |
| 278 | }}, |
| 279 | { 1, 1, "VMX inside of SMX operation", "R/WL", PRESENT_BIN, { |
| 280 | /* This bit enables a system executive to use |
Elyes HAOUAS | 75db5966 | 2018-08-23 18:16:26 +0200 | [diff] [blame] | 281 | * VMX in conjunction with SMX to support Intel |
Olivier Langlois | ccc7d1f | 2013-06-03 01:30:25 -0400 | [diff] [blame] | 282 | * Trusted Execution Technology. |
| 283 | */ |
| 284 | { MSR1(0), "VMX inside of SMX operation disabled" }, |
| 285 | { MSR1(1), "VMX inside of SMX operation enabled" }, |
| 286 | { BITVAL_EOT } |
| 287 | }}, |
| 288 | /* if CPUID.01H: ECX[5 or 6] = 1 */ |
| 289 | { 0, 1, "Lock bit", "R/WO", PRESENT_BIN, { |
| 290 | /* Once the Lock bit is set, the contents |
| 291 | * of this register cannot be modified. |
| 292 | * Therefore the lock bit must be set after |
| 293 | * configuring support for Intel Virtualization |
| 294 | * Technology and prior transferring control |
| 295 | * to an Option ROM or bootloader. Hence, once |
| 296 | * the lock bit is set, the entire IA32_FEATURE_CONTROL_MSR |
| 297 | * contents are preserved across RESET when |
| 298 | * PWRGOOD it not deasserted. |
| 299 | */ |
| 300 | { MSR1(0), "IA32_FEATURE_CONTROL MSR can be modified" }, |
| 301 | { MSR1(1), "IA32_FEATURE_CONTROL MSR cannot be modified" }, |
| 302 | { BITVAL_EOT } |
| 303 | }}, |
| 304 | { BITS_EOT } |
| 305 | }}, |
| 306 | {0x40, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_FROM_IP", "", { |
| 307 | { BITS_EOT } |
| 308 | }}, |
| 309 | {0x41, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_FROM_IP", "", { |
| 310 | { BITS_EOT } |
| 311 | }}, |
| 312 | {0x42, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_FROM_IP", "", { |
| 313 | { BITS_EOT } |
| 314 | }}, |
| 315 | {0x43, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_FROM_IP", "", { |
| 316 | { BITS_EOT } |
| 317 | }}, |
| 318 | {0x44, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_4_FROM_IP", "", { |
| 319 | { BITS_EOT } |
| 320 | }}, |
| 321 | {0x45, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_5_FROM_IP", "", { |
| 322 | { BITS_EOT } |
| 323 | }}, |
| 324 | {0x46, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_6_FROM_IP", "", { |
| 325 | { BITS_EOT } |
| 326 | }}, |
| 327 | {0x47, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_7_FROM_IP", "", { |
| 328 | { BITS_EOT } |
| 329 | }}, |
| 330 | {0x60, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_TO_LIP", "", { |
| 331 | { BITS_EOT } |
| 332 | }}, |
| 333 | {0x61, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_TO_LIP", "", { |
| 334 | { BITS_EOT } |
| 335 | }}, |
| 336 | {0x62, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_TO_LIP", "", { |
| 337 | { BITS_EOT } |
| 338 | }}, |
| 339 | {0x63, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_TO_LIP", "", { |
| 340 | { BITS_EOT } |
| 341 | }}, |
| 342 | {0x64, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_4_TO_LIP", "", { |
| 343 | { BITS_EOT } |
| 344 | }}, |
| 345 | {0x65, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_5_TO_LIP", "", { |
| 346 | { BITS_EOT } |
| 347 | }}, |
| 348 | {0x66, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_6_TO_LIP", "", { |
| 349 | { BITS_EOT } |
| 350 | }}, |
| 351 | {0x67, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_7_TO_LIP", "", { |
| 352 | { BITS_EOT } |
| 353 | }}, |
| 354 | {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", |
| 355 | "BIOS Update Signature ID (RO)", { |
| 356 | { BITS_EOT } |
| 357 | }}, |
| 358 | {0xc1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC0", |
| 359 | "Performance counter register", { |
| 360 | { BITS_EOT } |
| 361 | }}, |
| 362 | {0xc2, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC1", |
| 363 | "Performance counter register", { |
| 364 | { BITS_EOT } |
| 365 | }}, |
| 366 | {0xe7, MSRTYPE_RDWR, MSR2(0,0), "IA32_MPERF", "", { |
| 367 | { BITS_EOT } |
| 368 | }}, |
| 369 | {0xe8, MSRTYPE_RDWR, MSR2(0,0), "IA32_APERF", "", { |
| 370 | { BITS_EOT } |
| 371 | }}, |
| 372 | {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", { |
| 373 | { BITS_EOT } |
| 374 | }}, |
| 375 | {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", { |
| 376 | { BITS_EOT } |
| 377 | }}, |
| 378 | {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", { |
| 379 | { BITS_EOT } |
| 380 | }}, |
| 381 | {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", { |
| 382 | { 63, 61, RESERVED }, |
| 383 | { 2, 1, "MCIP", "R/W", PRESENT_BIN, { |
| 384 | /* When set, bit indicates that a machine check has been |
| 385 | * generated. If a second machine check is detected while |
| 386 | * this bit is still set, the processor enters a shutdown state. |
| 387 | * Software should write this bit to 0 after processing |
| 388 | * a machine check exception. |
| 389 | */ |
| 390 | { MSR1(0), "Nothing" }, |
| 391 | { MSR1(1), "Machine check has been generated" }, |
| 392 | { BITVAL_EOT } |
| 393 | }}, |
| 394 | { 1, 1, "EPIV", "R/W", PRESENT_BIN, { |
| 395 | /* When set, bit indicates that the instruction addressed |
| 396 | * by the instruction pointer pushed on the stack (when |
| 397 | * the machine check was generated) is directly associated |
| 398 | * with the error |
| 399 | */ |
| 400 | { MSR1(0), "Nothing" }, |
| 401 | { MSR1(1), "Instruction addressed directly associated with the error" }, |
| 402 | { BITVAL_EOT } |
| 403 | }}, |
| 404 | { 0, 1, "RIPV", "R/W", PRESENT_BIN, { |
| 405 | /* When set, bit indicates that the instruction addressed |
| 406 | * by the instruction pointer pushed on the stack (when |
| 407 | * the machine check was generated) can be used to restart |
| 408 | * the program. If cleared, the program cannot be reliably restarted |
| 409 | */ |
| 410 | { MSR1(0), "Program cannot be reliably restarted" }, |
| 411 | { MSR1(1), "Instruction addressed can be used to restart the program" }, |
| 412 | { BITVAL_EOT } |
| 413 | }}, |
| 414 | { BITS_EOT } |
| 415 | }}, |
| 416 | /* if CPUID.0AH: EAX[15:8] > 0 */ |
| 417 | {0x186, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL0", |
| 418 | "Performance Event Select Register 0", { |
| 419 | { 63, 32, RESERVED }, |
| 420 | { 31, 8, "CMASK", "R/W", PRESENT_HEX, { |
| 421 | /* When CMASK is not zero, the corresponding performance |
| 422 | * counter 0 increments each cycle if the event count |
| 423 | * is greater than or equal to the CMASK. |
| 424 | */ |
| 425 | { BITVAL_EOT } |
| 426 | }}, |
| 427 | { 23, 1, "INV", "R/W", PRESENT_BIN, { |
| 428 | { MSR1(0), "CMASK using as is" }, |
| 429 | { MSR1(1), "CMASK inerting" }, |
| 430 | { BITVAL_EOT } |
| 431 | }}, |
| 432 | { 22, 1, "EN", "R/W", PRESENT_BIN, { |
| 433 | { MSR1(0), "No commence counting" }, |
| 434 | { MSR1(1), "Commence counting" }, |
| 435 | { BITVAL_EOT } |
| 436 | }}, |
| 437 | { 21, 1, "AnyThread", "R/W", PRESENT_BIN, { |
| 438 | { BITVAL_EOT } |
| 439 | }}, |
| 440 | { 20, 1, "INT", "R/W", PRESENT_BIN, { |
| 441 | { MSR1(0), "Interrupt on counter overflow is disabled" }, |
| 442 | { MSR1(1), "Interrupt on counter overflow is enabled" }, |
| 443 | { BITVAL_EOT } |
| 444 | }}, |
| 445 | { 19, 1, "PC", "R/W", PRESENT_BIN, { |
| 446 | { MSR1(0), "Disabled pin control" }, |
| 447 | { MSR1(1), "Enabled pin control" }, |
| 448 | { BITVAL_EOT } |
| 449 | }}, |
| 450 | { 18, 1, "Edge", "R/W", PRESENT_BIN, { |
| 451 | { MSR1(0), "Disabled edge detection" }, |
| 452 | { MSR1(1), "Enabled edge detection" }, |
| 453 | { BITVAL_EOT } |
| 454 | }}, |
| 455 | { 17, 1, "OS", "R/W", PRESENT_BIN, { |
| 456 | { MSR1(0), "Nothing" }, |
| 457 | { MSR1(1), "Counts while in privilege level is ring 0" }, |
| 458 | { BITVAL_EOT } |
| 459 | }}, |
| 460 | { 16, 1, "USR", "R/W", PRESENT_BIN, { |
| 461 | { MSR1(0), "Nothing" }, |
| 462 | { MSR1(1), "Counts while in privilege level is not ring 0" }, |
| 463 | { BITVAL_EOT } |
| 464 | }}, |
| 465 | { 15, 8, "UMask", "R/W", PRESENT_HEX, { |
| 466 | /* Qualifies the microarchitectural condition |
| 467 | * to detect on the selected event logic. */ |
| 468 | { BITVAL_EOT } |
| 469 | }}, |
| 470 | { 7, 8, "Event Select", "R/W", PRESENT_HEX, { |
| 471 | /* Selects a performance event logic unit. */ |
| 472 | { BITVAL_EOT } |
| 473 | }}, |
| 474 | { BITS_EOT } |
| 475 | }}, |
| 476 | /* if CPUID.0AH: EAX[15:8] > 0 */ |
| 477 | {0x187, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL1", |
| 478 | "Performance Event Select Register 1", { |
| 479 | { 63, 32, RESERVED }, |
| 480 | { 31, 8, "CMASK", "R/W", PRESENT_HEX, { |
| 481 | /* When CMASK is not zero, the corresponding performance |
| 482 | * counter 1 increments each cycle if the event count |
| 483 | * is greater than or equal to the CMASK. |
| 484 | */ |
| 485 | { BITVAL_EOT } |
| 486 | }}, |
| 487 | { 23, 1, "INV", "R/W", PRESENT_BIN, { |
| 488 | { MSR1(0), "CMASK using as is" }, |
| 489 | { MSR1(1), "CMASK inerting" }, |
| 490 | { BITVAL_EOT } |
| 491 | }}, |
| 492 | { 22, 1, "EN", "R/W", PRESENT_BIN, { |
| 493 | { MSR1(0), "No commence counting" }, |
| 494 | { MSR1(1), "Commence counting" }, |
| 495 | { BITVAL_EOT } |
| 496 | }}, |
| 497 | { 21, 1, "AnyThread", "R/W", PRESENT_BIN, { |
| 498 | { BITVAL_EOT } |
| 499 | }}, |
| 500 | { 20, 1, "INT", "R/W", PRESENT_BIN, { |
| 501 | { MSR1(0), "Interrupt on counter overflow is disabled" }, |
| 502 | { MSR1(1), "Interrupt on counter overflow is enabled" }, |
| 503 | { BITVAL_EOT } |
| 504 | }}, |
| 505 | { 19, 1, "PC", "R/W", PRESENT_BIN, { |
| 506 | { MSR1(0), "Disabled pin control" }, |
| 507 | { MSR1(1), "Enabled pin control" }, |
| 508 | { BITVAL_EOT } |
| 509 | }}, |
| 510 | { 18, 1, "Edge", "R/W", PRESENT_BIN, { |
| 511 | { MSR1(0), "Disabled edge detection" }, |
| 512 | { MSR1(1), "Enabled edge detection" }, |
| 513 | { BITVAL_EOT } |
| 514 | }}, |
| 515 | { 17, 1, "OS", "R/W", PRESENT_BIN, { |
| 516 | { MSR1(0), "Nothing" }, |
| 517 | { MSR1(1), "Counts while in privilege level is ring 0" }, |
| 518 | { BITVAL_EOT } |
| 519 | }}, |
| 520 | { 16, 1, "USR", "R/W", PRESENT_BIN, { |
| 521 | { MSR1(0), "Nothing" }, |
| 522 | { MSR1(1), "Counts while in privilege level is not ring 0" }, |
| 523 | { BITVAL_EOT } |
| 524 | }}, |
| 525 | { 15, 8, "UMask", "R/W", PRESENT_HEX, { |
| 526 | /* Qualifies the microarchitectural condition |
| 527 | * to detect on the selected event logic. */ |
| 528 | { BITVAL_EOT } |
| 529 | }}, |
| 530 | { 7, 8, "Event Select", "R/W", PRESENT_HEX, { |
| 531 | /* Selects a performance event logic unit. */ |
| 532 | { BITVAL_EOT } |
| 533 | }}, |
| 534 | { BITS_EOT } |
| 535 | }}, |
| 536 | {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CTL", "", { |
| 537 | { BITS_EOT } |
| 538 | }}, |
| 539 | {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", |
| 540 | "Clock Modulation", { |
| 541 | { 63, 59, RESERVED }, |
| 542 | { 4, 1, "On demand Clock Modulation", "R/W", PRESENT_BIN, { |
| 543 | { MSR1(0), "On demand Clock Modulation is disabled" }, |
| 544 | { MSR1(1), "On demand Clock Modulation is enabled" }, |
| 545 | { BITVAL_EOT } |
| 546 | }}, |
| 547 | { 3, 3, "On demand Clock Modulation Duty Cycle", "R/W", PRESENT_HEX, { |
| 548 | { BITVAL_EOT } |
| 549 | }}, |
| 550 | { 0, 1, RESERVED }, |
| 551 | { BITS_EOT } |
| 552 | }}, |
| 553 | {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", |
| 554 | "Thermal Interrupt Control", { |
| 555 | { BITS_EOT } |
| 556 | }}, |
| 557 | {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", |
| 558 | "Thermal Monitor Status", { |
| 559 | { BITS_EOT } |
| 560 | }}, |
| 561 | {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", |
| 562 | "Enable miscellaneous processor features", { |
| 563 | { 63, 25, RESERVED }, |
| 564 | /* Note: [38] bit using for whole package, |
| 565 | * while some other bits can be Core or Thread |
| 566 | * specific. |
| 567 | */ |
| 568 | { 38, 1, "Turbo Mode", "R/W", PRESENT_BIN, { |
| 569 | /* When set to a 0 on processors that support IDA, |
| 570 | * CPUID.06H: EAX[1] reports the processor's |
| 571 | * support of turbo mode is enabled. |
| 572 | */ |
| 573 | { MSR1(0), "Turbo Mode enabled" }, |
| 574 | /* When set 1 on processors that support Intel Turbo Boost |
| 575 | * technology, the turbo mode feature is disabled and |
| 576 | * the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0). |
| 577 | */ |
| 578 | { MSR1(1), "Turbo Mode disabled" }, |
| 579 | { BITVAL_EOT } |
| 580 | /* Note: the power-on default value is used by BIOS to detect |
| 581 | * hardware support of turbo mode. If power-on default value is 1, |
| 582 | * turbo mode is available in the processor. If power-on default |
| 583 | * value is 0, turbo mode not available. |
| 584 | */ |
| 585 | }}, |
| 586 | { 37, 3, RESERVED }, |
| 587 | { 34, 1, "XD Bit Disable", "R/W", PRESENT_BIN, { |
| 588 | { BITVAL_EOT } |
| 589 | }}, |
| 590 | { 33, 10, RESERVED }, |
| 591 | { 23, 1, "xTPR Message Disable", "R/W", PRESENT_BIN, { |
| 592 | { BITVAL_EOT } |
| 593 | }}, |
| 594 | { 22, 1, "Limit CPUID Maxval", "R/W", PRESENT_BIN, { |
| 595 | { BITVAL_EOT } |
| 596 | }}, |
| 597 | { 21, 3, RESERVED }, |
| 598 | { 18, 1, "Enable Monitor FSM", "R/W", PRESENT_BIN, { |
| 599 | { BITVAL_EOT } |
| 600 | }}, |
| 601 | { 17, 1, "UNDOCUMENTED", "R/W", PRESENT_BIN, { |
| 602 | { BITVAL_EOT } |
| 603 | }}, |
| 604 | /* Note: [16] bit using for whole package, |
| 605 | * while some other bits can be Core or Thread |
| 606 | * specific. |
| 607 | */ |
| 608 | { 16, 1, "Enhanced Intel SpeedStep Technology Enable", "R/W", |
| 609 | PRESENT_BIN, { |
| 610 | { BITVAL_EOT } |
| 611 | }}, |
| 612 | { 15, 3, RESERVED }, |
| 613 | { 12, 1, "Precise Event Based Sampling Unavailable", "R/O", |
| 614 | PRESENT_BIN, { |
| 615 | { BITVAL_EOT } |
| 616 | }}, |
| 617 | { 11, 1, "Branch Trace Storage Unavailable", "R/O", PRESENT_BIN, { |
| 618 | { BITVAL_EOT } |
| 619 | }}, |
| 620 | { 10, 3, RESERVED }, |
| 621 | { 7, 1, "Performance Monitoring Available", "R", PRESENT_BIN, { |
| 622 | { BITVAL_EOT } |
| 623 | }}, |
| 624 | { 6, 3, RESERVED }, |
| 625 | { 3, 1, "Automatic Thermal Control Circuit Enable", "R/W" |
| 626 | , PRESENT_BIN, { |
| 627 | { BITVAL_EOT } |
| 628 | }}, |
| 629 | { 2, 2, RESERVED }, |
| 630 | { 0, 1, "Fast-Strings Enable", "R/W", PRESENT_BIN, { |
| 631 | { BITVAL_EOT } |
| 632 | }}, |
| 633 | { BITS_EOT } |
| 634 | }}, |
| 635 | {0x1c9, MSRTYPE_RDONLY, MSR2(0,0), "MSR_LASTBRANCH_TOS", |
| 636 | "Last Branch Record Stack TOS", { |
| 637 | /* Contains an index (bits 0-3) that points to the MSR containing |
| 638 | * the most recent branch record. See also MSR_LASTBRANCH_0_FROM_IP (0x680). |
| 639 | */ |
| 640 | { BITS_EOT } |
| 641 | }}, |
| 642 | {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", |
| 643 | "Debug/Trace/Profile Resource Control", { |
| 644 | /* (MSR_DEBUGCTTLA, MSR_DEBUGCTLB) */ |
| 645 | { 63, 49, RESERVED }, |
| 646 | /* Only if IA32_PERF_CAPABILITIES[12] = 1 */ |
| 647 | { 14, 1, "FREEZE_WHILE_SMM", "R/O", PRESENT_BIN, { |
| 648 | { MSR1(0), "Nothing" }, |
| 649 | { MSR1(1), "Freeze perfmon and trace messages while in SMM" }, |
| 650 | { BITVAL_EOT } |
| 651 | }}, |
| 652 | { 13, 1, "ENABLE_UNCORE_PMI", "R/O", PRESENT_BIN, { |
| 653 | { MSR1(0), "Nothing" }, |
| 654 | { MSR1(1), "Logical processor can receive and generate PMI \ |
| 655 | on behalf of the uncore" }, |
| 656 | { BITVAL_EOT } |
| 657 | }}, |
| 658 | /* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */ |
| 659 | { 12, 1, "FREEZE_PERFMON_ON_PMI", "R/O", PRESENT_BIN, { |
| 660 | { MSR1(0), "Nothing" }, |
| 661 | { MSR1(1), "Each ENABLE bit of the global counter control MSR \ |
| 662 | are frozen (address 0x3bf) on PMI request" }, |
| 663 | { BITVAL_EOT } |
| 664 | }}, |
| 665 | /* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */ |
| 666 | { 11, 1, "FREEZE_LBRS_ON_PMI", "R/O", PRESENT_BIN, { |
| 667 | { MSR1(0), "Nothing" }, |
| 668 | { MSR1(1), "LBR stack is frozen on PMI request" }, |
| 669 | { BITVAL_EOT } |
| 670 | }}, |
| 671 | { 10, 1, "BTS_OFF_USR", "R/O", PRESENT_BIN, { |
| 672 | { MSR1(0), "Nothing" }, |
| 673 | { MSR1(1), "BTS or BTM is skipped if CPL > 0" }, |
| 674 | { BITVAL_EOT } |
| 675 | }}, |
| 676 | { 9, 1, "BTS_OFF_OS", "R/O", PRESENT_BIN, { |
| 677 | { MSR1(0), "Nothing" }, |
| 678 | { MSR1(1), "BTS or BTM is skipped if CPL = 0" }, |
| 679 | { BITVAL_EOT } |
| 680 | }}, |
| 681 | { 8, 1, "BTINT", "R/O", PRESENT_BIN, { |
| 682 | { MSR1(0), "BTMs are logged in a BTS buffer in circular fashion" }, |
| 683 | { MSR1(1), "An interrupt is generated by the BTS facility \ |
| 684 | when the BTS buffer is full" }, |
| 685 | { BITVAL_EOT } |
| 686 | }}, |
| 687 | { 7, 1, "BTS", "R/O", PRESENT_BIN, { |
| 688 | { MSR1(0), "Logging of BTMs (branch trace messages) \ |
| 689 | in BTS buffer is disabled" }, |
| 690 | { MSR1(1), "Logging of BTMs (branch trace messages) \ |
| 691 | in BTS buffer is enabled" }, |
| 692 | { BITVAL_EOT } |
| 693 | }}, |
| 694 | { 6, 1, "TR", "R/O", PRESENT_BIN, { |
| 695 | { MSR1(0), "Branch trace messages are disabled" }, |
| 696 | { MSR1(1), "Branch trace messages are enabled" }, |
| 697 | { BITVAL_EOT } |
| 698 | }}, |
| 699 | { 5, 4, RESERVED }, |
| 700 | { 1, 1, "BTF", "R/O", PRESENT_BIN, { |
| 701 | { MSR1(0), "Nothing" }, |
| 702 | { MSR1(1), "Enabled treating EFLAGS.TF as single-step on \ |
| 703 | branches instead of single-step on instructions" }, |
| 704 | { BITVAL_EOT } |
| 705 | }}, |
| 706 | { 0, 1, "LBR", "R/O", PRESENT_BIN, { |
| 707 | { MSR1(0), "Nothing" }, |
| 708 | { MSR1(1), "Enabled recording a running trace of the most \ |
| 709 | recent branches taken by the processor in the LBR stack" }, |
| 710 | { BITVAL_EOT } |
| 711 | }}, |
| 712 | { BITS_EOT } |
| 713 | }}, |
| 714 | {0x1dd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_LER_FROM_LIP", |
| 715 | "Last Exception Record From Linear IP", { |
| 716 | /* Contains a pointer to the last branch instruction |
| 717 | * that the processor executed prior to the last exception |
| 718 | * that was generated or the last interrupt that was handled. |
| 719 | */ |
| 720 | { BITS_EOT } |
| 721 | }}, |
| 722 | {0x1de, MSRTYPE_RDONLY, MSR2(0,0), "MSR_LER_TO_LIP", |
| 723 | "Last Exception Record To Linear IP", { |
| 724 | /* This area contains a pointer to the target of the |
| 725 | * last branch instruction that the processor executed |
| 726 | * prior to the last exception that was generated or |
| 727 | * the last interrupt that was handled |
| 728 | */ |
| 729 | { BITS_EOT } |
| 730 | }}, |
| 731 | {0x277, MSRTYPE_RDWR, MSR2(0,0), "IA32_PAT", "IA32_PAT", { |
| 732 | { 63, 5, RESERVED }, |
| 733 | { 58, 3, "PA7", "R/W", PRESENT_BIN, { |
| 734 | { BITVAL_EOT } |
| 735 | }}, |
| 736 | { 55, 5, RESERVED }, |
| 737 | { 40, 3, "PA6", "R/W", PRESENT_BIN, { |
| 738 | { BITVAL_EOT } |
| 739 | }}, |
| 740 | { 47, 5, RESERVED }, |
| 741 | { 42, 3, "PA5", "R/W", PRESENT_BIN, { |
| 742 | { BITVAL_EOT } |
| 743 | }}, |
| 744 | { 39, 5, RESERVED }, |
| 745 | { 34, 3, "PA4", "R/W", PRESENT_BIN, { |
| 746 | { BITVAL_EOT } |
| 747 | }}, |
| 748 | { 31, 5, RESERVED }, |
| 749 | { 26, 3, "PA3", "R/W", PRESENT_BIN, { |
| 750 | { BITVAL_EOT } |
| 751 | }}, |
| 752 | { 23, 5, RESERVED }, |
| 753 | { 18, 3, "PA2", "R/W", PRESENT_BIN, { |
| 754 | { BITVAL_EOT } |
| 755 | }}, |
| 756 | { 15, 5, RESERVED }, |
| 757 | { 10, 3, "PA1", "R/W", PRESENT_BIN, { |
| 758 | { BITVAL_EOT } |
| 759 | }}, |
| 760 | { 7, 5, RESERVED }, |
| 761 | { 2, 3, "PA0", "R/W", PRESENT_BIN, { |
| 762 | { BITVAL_EOT } |
| 763 | }}, |
| 764 | { BITS_EOT } |
| 765 | }}, |
| 766 | /* if CPUID.0AH: EDX[4:0] > 0 */ |
| 767 | {0x309, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR0", "Fixed-Function \ |
| 768 | Performance Counter Register 0: Counts Instr_Retired.Any", { |
| 769 | /* Also known as MSR_PERF_FIXED_CTR0 */ |
| 770 | { BITS_EOT } |
| 771 | }}, |
| 772 | /* if CPUID.0AH: EDX[4:0] > 1 */ |
| 773 | {0x30a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR1", "Fixed-Function \ |
| 774 | Performance Counter Register 1: Counts CPU_CLK_Unhalted.Core ", { |
| 775 | /* Also known as MSR_PERF_FIXED_CTR1 */ |
| 776 | { BITS_EOT } |
| 777 | }}, |
| 778 | /* if CPUID.0AH: EDX[4:0] > 2 */ |
| 779 | {0x30b, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR2", "Fixed-Function \ |
| 780 | Performance Counter Register 2: Counts CPU_CLK_Unhalted.Ref", { |
| 781 | /* Also known as MSR_PERF_FIXED_CTR2 */ |
| 782 | { BITS_EOT } |
| 783 | }}, |
| 784 | /* if CPUID.0AH: EAX[7:0] > 1*/ |
| 785 | {0x38d, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR_CTRL", |
| 786 | "Fixed-Function-Counter Control Register", { |
| 787 | /* Also known as MSR_PERF_FIXED_CTR_CTRL. |
| 788 | * Counter increments while the results of ANDing respective enable bit |
| 789 | * in IA32_PERF_GLOBAL_CTRL with the corresponding OS or USR bits |
| 790 | * in this MSR is true. */ |
| 791 | { 63, 52, RESERVED }, |
| 792 | { 11, 1, "EN2_PMI", "R/W", PRESENT_BIN, { |
| 793 | { MSR1(0), "Nothing" }, |
| 794 | { MSR1(1), "PMI when fixed counter 2 overflows is enabled" }, |
| 795 | { BITVAL_EOT } |
| 796 | }}, |
| 797 | /* if CPUID.0AH EAX[7:0] > 2 */ |
| 798 | { 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, { |
| 799 | { MSR1(0), "Counter only increments the associated event \ |
Elyes HAOUAS | 75db5966 | 2018-08-23 18:16:26 +0200 | [diff] [blame] | 800 | conditions occurring in the logical processor which programmed the MSR" }, |
Olivier Langlois | ccc7d1f | 2013-06-03 01:30:25 -0400 | [diff] [blame] | 801 | { MSR1(1), "Counting the associated event conditions \ |
Elyes HAOUAS | 75db5966 | 2018-08-23 18:16:26 +0200 | [diff] [blame] | 802 | occurring across all logical processors sharing a processor core" }, |
Olivier Langlois | ccc7d1f | 2013-06-03 01:30:25 -0400 | [diff] [blame] | 803 | { BITVAL_EOT } |
| 804 | }}, |
| 805 | { 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, { |
| 806 | { MSR1(0), "Nothing" }, |
| 807 | { MSR1(1), "Fixed counter 2 is enabled to count while CPL > 0" }, |
| 808 | { BITVAL_EOT } |
| 809 | }}, |
| 810 | { 8, 1, "EN2_OS", "R/W", PRESENT_BIN, { |
| 811 | { MSR1(0), "Nothing" }, |
| 812 | { MSR1(1), "Fixed counter 2 is enabled to count while CPL = 0" }, |
| 813 | { BITVAL_EOT } |
| 814 | }}, |
| 815 | { 7, 1, "EN1_PMI", "R/W", PRESENT_BIN, { |
| 816 | { MSR1(0), "Nothing" }, |
| 817 | { MSR1(1), "PMI when fixed counter 1 overflows is enabled" }, |
| 818 | { BITVAL_EOT } |
| 819 | }}, |
| 820 | /* if CPUID.0AH: EAX[7:0] > 2 */ |
| 821 | { 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, { |
| 822 | { MSR1(0), "Counter only increments the associated event \ |
Elyes HAOUAS | 75db5966 | 2018-08-23 18:16:26 +0200 | [diff] [blame] | 823 | conditions occurring in the logical processor which programmed the MSR" }, |
Olivier Langlois | ccc7d1f | 2013-06-03 01:30:25 -0400 | [diff] [blame] | 824 | { MSR1(1), "Counting the associated event conditions \ |
Elyes HAOUAS | 75db5966 | 2018-08-23 18:16:26 +0200 | [diff] [blame] | 825 | occurring across all logical processors sharing a processor core" }, |
Olivier Langlois | ccc7d1f | 2013-06-03 01:30:25 -0400 | [diff] [blame] | 826 | { BITVAL_EOT } |
| 827 | }}, |
| 828 | { 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, { |
| 829 | { MSR1(0), "Nothing" }, |
| 830 | { MSR1(1), "Fixed counter 1 is enabled to count while CPL > 0" }, |
| 831 | { BITVAL_EOT } |
| 832 | }}, |
| 833 | { 4, 1, "EN1_OS", "R/W", PRESENT_BIN, { |
| 834 | { MSR1(0), "Nothing" }, |
| 835 | { MSR1(1), "Fixed counter 1 is enabled to count while CPL = 0" }, |
| 836 | { BITVAL_EOT } |
| 837 | }}, |
| 838 | { 3, 1, "EN0_PMI", "R/W", PRESENT_BIN, { |
| 839 | { MSR1(0), "Nothing" }, |
| 840 | { MSR1(1), "PMI when fixed counter 0 overflows is enabled" }, |
| 841 | { BITVAL_EOT } |
| 842 | }}, |
| 843 | /* if CPUID.0AH: EAX[7:0] > 2 */ |
| 844 | { 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, { |
| 845 | { MSR1(0), "Counter only increments the associated event \ |
Elyes HAOUAS | 75db5966 | 2018-08-23 18:16:26 +0200 | [diff] [blame] | 846 | conditions occurring in the logical processor which programmed the MSR" }, |
Olivier Langlois | ccc7d1f | 2013-06-03 01:30:25 -0400 | [diff] [blame] | 847 | { MSR1(1), "Counting the associated event conditions \ |
Elyes HAOUAS | 75db5966 | 2018-08-23 18:16:26 +0200 | [diff] [blame] | 848 | occurring across all logical processors sharing a processor core" }, |
Olivier Langlois | ccc7d1f | 2013-06-03 01:30:25 -0400 | [diff] [blame] | 849 | { BITVAL_EOT } |
| 850 | }}, |
| 851 | { 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, { |
| 852 | { MSR1(0), "Nothing" }, |
| 853 | { MSR1(1), "Fixed counter 0 is enabled to count while CPL > 0" }, |
| 854 | { BITVAL_EOT } |
| 855 | }}, |
| 856 | { 0, 1, "EN0_OS", "R/W", PRESENT_BIN, { |
| 857 | { MSR1(0), "Nothing" }, |
| 858 | { MSR1(1), "Fixed counter 0 is enabled to count while CPL = 0" }, |
| 859 | { BITVAL_EOT } |
| 860 | }}, |
| 861 | { BITS_EOT } |
| 862 | }}, |
| 863 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 864 | {0x38e, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_GLOBAL_STATUS", |
| 865 | "Global Performance Counter Status", { |
| 866 | /* Also known as MSR_PERF_GLOBAL_STATUS */ |
| 867 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 868 | { 63, 1, "CondChg: Status bits of this register has changed", |
| 869 | "R/O", PRESENT_BIN, { |
| 870 | { BITVAL_EOT } |
| 871 | }}, |
| 872 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 873 | { 62, 1, "OvfBuf: DS SAVE area Buffer overflow status", |
| 874 | "R/O", PRESENT_BIN, { |
| 875 | { BITVAL_EOT } |
| 876 | }}, |
| 877 | /* if CPUID.0AH: EAX[7:0] > 2 */ |
| 878 | { 61, 1, "Ovf_Uncore: Uncore counter overflow status", |
| 879 | "R/O", PRESENT_BIN, { |
| 880 | { BITVAL_EOT } |
| 881 | }}, |
| 882 | { 60, 26, RESERVED }, |
| 883 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 884 | { 34, 1, "Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2", |
| 885 | "R/O", PRESENT_BIN, { |
| 886 | { BITVAL_EOT } |
| 887 | }}, |
| 888 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 889 | { 33, 1, "Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1", |
| 890 | "R/O", PRESENT_BIN, { |
| 891 | { BITVAL_EOT } |
| 892 | }}, |
| 893 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 894 | { 32, 1, "Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0", |
| 895 | "R/O", PRESENT_BIN, { |
| 896 | { BITVAL_EOT } |
| 897 | }}, |
| 898 | { 31, 28, RESERVED }, |
| 899 | /* presented only in 06_2EH Nehalem model */ |
| 900 | { 3, 1, "Ovf_PMC3: Overflow status of IA32_PMC3", "R/O", PRESENT_BIN, { |
| 901 | { BITVAL_EOT } |
| 902 | }}, |
| 903 | /* presented only in 06_2EH Nehalem model */ |
| 904 | { 2, 1, "Ovf_PMC2: Overflow status of IA32_PMC2", "R/O", PRESENT_BIN, { |
| 905 | { BITVAL_EOT } |
| 906 | }}, |
| 907 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 908 | { 1, 1, "Ovf_PMC1: Overflow status of IA32_PMC1", "R/O", PRESENT_BIN, { |
| 909 | { BITVAL_EOT } |
| 910 | }}, |
| 911 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 912 | { 0, 1, "Ovf_PMC0: Overflow status of IA32_PMC0", "R/O", PRESENT_BIN, { |
| 913 | { BITVAL_EOT } |
| 914 | }}, |
| 915 | { BITS_EOT } |
| 916 | }}, |
| 917 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 918 | {0x38f, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_CTL", |
| 919 | "Global Performance Counter Control", { |
| 920 | /* Counter increments while the result of ANDing respective |
| 921 | * enable bit in this MSR with corresponding OS or USR bits |
| 922 | * in general-purpose or fixed counter control MSR is true. |
| 923 | */ |
| 924 | { 63, 29, RESERVED }, |
| 925 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 926 | { 34, 1, "EN_FIXED_CTR2", "R/W", PRESENT_BIN, { |
| 927 | { BITVAL_EOT } |
| 928 | }}, |
| 929 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 930 | { 33, 1, "EN_FIXED_CTR1", "R/W", PRESENT_BIN, { |
| 931 | { BITVAL_EOT } |
| 932 | }}, |
| 933 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 934 | { 32, 1, "EN_FIXED_CTR0", "R/W", PRESENT_BIN, { |
| 935 | { BITVAL_EOT } |
| 936 | }}, |
| 937 | { 31, 30, RESERVED }, |
| 938 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 939 | { 1, 1, "EN_PMC1", "R/W", PRESENT_BIN, { |
| 940 | { BITVAL_EOT } |
| 941 | }}, |
| 942 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 943 | { 0, 1, "EN_PMC0", "R/W", PRESENT_BIN, { |
| 944 | { BITVAL_EOT } |
| 945 | }}, |
| 946 | { BITS_EOT } |
| 947 | }}, |
| 948 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 949 | {0x390, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_OVF_CTL", |
| 950 | "Global Performance Counter Overflow Control", { |
| 951 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 952 | { 63, 1, "Clear CondChg bit", "R/W", PRESENT_BIN, { |
| 953 | { BITVAL_EOT } |
| 954 | }}, |
| 955 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 956 | { 62, 1, "Clear OvfBuf bit", "R/W", PRESENT_BIN, { |
| 957 | { BITVAL_EOT } |
| 958 | }}, |
| 959 | /* Presented only in 06_2EH Nehalem model */ |
| 960 | { 61, 1, "Clear Ovf_Uncore bit", "R/W", PRESENT_BIN, { |
| 961 | { BITVAL_EOT } |
| 962 | }}, |
| 963 | { 60, 26, RESERVED }, |
| 964 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 965 | { 34, 1, "Clear Ovf_FIXED_CTR2 bit", "R/W", PRESENT_BIN, { |
| 966 | { BITVAL_EOT } |
| 967 | }}, |
| 968 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 969 | { 33, 1, "Clear Ovf_FIXED_CTR1 bit", "R/W", PRESENT_BIN, { |
| 970 | { BITVAL_EOT } |
| 971 | }}, |
| 972 | /* if CPUID.0AH: EAX[7:0] > 1 */ |
| 973 | { 32, 1, "Clear Ovf_FIXED_CTR0 bit", "R/W", PRESENT_BIN, { |
| 974 | { BITVAL_EOT } |
| 975 | }}, |
| 976 | { 31, 30, RESERVED }, |
| 977 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 978 | { 1, 1, "Clear Ovf_PMC1 bit", "R/W", PRESENT_BIN, { |
| 979 | { BITVAL_EOT } |
| 980 | }}, |
| 981 | /* if CPUID.0AH: EAX[7:0] > 0 */ |
| 982 | { 0, 1, "Clear Ovf_PMC0 bit", "R/W", PRESENT_BIN, { |
| 983 | { BITVAL_EOT } |
| 984 | }}, |
| 985 | { BITS_EOT } |
| 986 | }}, |
| 987 | /* See Section 18.6.1.1 of Intel 64 and IA-32 Architectures |
| 988 | * Software Developer's Manual, Volume 3, |
| 989 | * "Precise Event Based Sampling (PEBS)". |
| 990 | */ |
| 991 | {0x3f1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PEBS_ENABLE", "PEBS Control", { |
| 992 | { 63, 28, RESERVED }, |
| 993 | { 35, 1, "Load Latency on IA32_PMC3", "R/W", PRESENT_BIN, { |
| 994 | { MSR1(0), "Disabled" }, |
| 995 | { MSR1(1), "Enabled" }, |
| 996 | { BITVAL_EOT } |
| 997 | }}, |
| 998 | { 34, 1, "Load Latency on IA32_PMC2", "R/W", PRESENT_BIN, { |
| 999 | { MSR1(0), "Disabled" }, |
| 1000 | { MSR1(1), "Enabled" }, |
| 1001 | { BITVAL_EOT } |
| 1002 | }}, |
| 1003 | { 33, 1, "Load Latency on IA32_PMC1", "R/W", PRESENT_BIN, { |
| 1004 | { MSR1(0), "Disabled" }, |
| 1005 | { MSR1(1), "Enabled" }, |
| 1006 | { BITVAL_EOT } |
| 1007 | }}, |
| 1008 | { 32, 1, "Load Latency on IA32_PMC0", "R/W", PRESENT_BIN, { |
| 1009 | { MSR1(0), "Disabled" }, |
| 1010 | { MSR1(1), "Enabled" }, |
| 1011 | { BITVAL_EOT } |
| 1012 | }}, |
| 1013 | { 31, 28, RESERVED }, |
| 1014 | { 3, 1, "PEBS on IA32_PMC3", "R/W", PRESENT_BIN, { |
| 1015 | { MSR1(0), "Disabled" }, |
| 1016 | { MSR1(1), "Enabled" }, |
| 1017 | { BITVAL_EOT } |
| 1018 | }}, |
| 1019 | { 2, 1, "PEBS on IA32_PMC2", "R/W", PRESENT_BIN, { |
| 1020 | { MSR1(0), "Disabled" }, |
| 1021 | { MSR1(1), "Enabled" }, |
| 1022 | { BITVAL_EOT } |
| 1023 | }}, |
| 1024 | { 1, 1, "PEBS on IA32_PMC1", "R/W", PRESENT_BIN, { |
| 1025 | { MSR1(0), "Disabled" }, |
| 1026 | { MSR1(1), "Enabled" }, |
| 1027 | { BITVAL_EOT } |
| 1028 | }}, |
| 1029 | { 0, 1, "PEBS on IA32_PMC0", "R/W", PRESENT_BIN, { |
| 1030 | { MSR1(0), "Disabled" }, |
| 1031 | { MSR1(1), "Enabled" }, |
| 1032 | { BITVAL_EOT } |
| 1033 | }}, |
| 1034 | { BITS_EOT } |
| 1035 | }}, |
| 1036 | #if 0 |
| 1037 | {0x480, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_BASIC", |
| 1038 | "Reporting Register of Basic VMX Capabilities", { |
| 1039 | /* Additional info available at |
| 1040 | * Appendix A.1, "Basic VMX Information" */ |
| 1041 | { 63, 10, RESERVED }, |
| 1042 | { 53, 4, "Memory type for VMREAD and VMWRITE", "R/O", PRESENT_HEX, { |
| 1043 | { BITVAL_EOT } |
| 1044 | }}, |
| 1045 | { 49, 1, "Support of dual-treatment of system-management functions", |
| 1046 | "R/O", PRESENT_BIN, { |
| 1047 | { BITVAL_EOT } |
| 1048 | }}, |
| 1049 | { 48, 1, "Enable full linear address access", "R/O", PRESENT_BIN, { |
| 1050 | { BITVAL_EOT } |
| 1051 | }}, |
| 1052 | { 47, 3, RESERVED }, |
| 1053 | { 44, 13, "VMXON region allocation size", "R/O", PRESENT_DEC, { |
| 1054 | { BITVAL_EOT } |
| 1055 | }}, |
| 1056 | { 31, 32, "VMCS Revision Identifier", "R/O", PRESENT_HEX, { |
| 1057 | { BITVAL_EOT } |
| 1058 | }}, |
| 1059 | { BITS_EOT } |
| 1060 | }}, |
| 1061 | {0x481, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PINBASED_CTLS", |
| 1062 | "Capability Reporting Register of \ |
| 1063 | Pin-based VM-execution Controls", { |
| 1064 | /* Additional info available at Appendix A.3, |
| 1065 | * "VM-Execution Controls" */ |
| 1066 | { BITS_EOT } |
| 1067 | }}, |
| 1068 | {0x482, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PROCBASED_CTLS", |
| 1069 | "Capability Reporting Register of \ |
| 1070 | Primary Processor-based VM-execution Controls", { |
| 1071 | /* Additional info available at Appendix A.3, |
| 1072 | * "VM-Execution Controls" */ |
| 1073 | { BITS_EOT } |
| 1074 | }}, |
| 1075 | {0x483, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_EXIT_CTLS", |
| 1076 | "Capability Reporting Register of VM-exit Controls", { |
| 1077 | /* Additional info available at Appendix A.4, |
| 1078 | * "VM-Exit Controls" */ |
| 1079 | { BITS_EOT } |
| 1080 | }}, |
| 1081 | {0x484, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_ENTRY_CTLS", |
| 1082 | "Capability Reporting Register of VM-entry Controls", { |
| 1083 | /* Additional info available at Appendix A.5, |
| 1084 | * "VM-Entry Controls" */ |
| 1085 | { BITS_EOT } |
| 1086 | }}, |
| 1087 | {0x485, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_MISC", |
| 1088 | "Reporting Register of Miscellaneous VMX Capabilities", { |
| 1089 | /* Additional info available at Appendix A.6, |
| 1090 | * "Miscellaneous Data" */ |
| 1091 | { BITS_EOT } |
| 1092 | }}, |
| 1093 | {0x486, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR0_FIXED0", |
| 1094 | "Capability Reporting Register of CR0 Bits Fixed to 0", { |
| 1095 | /* Additional info available at Appendix A.7, |
| 1096 | * "VMX-Fixed Bits in CR0" */ |
| 1097 | { BITS_EOT } |
| 1098 | }}, |
| 1099 | {0x487, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR0_FIXED1", |
| 1100 | "Capability Reporting Register of CR0 Bits Fixed to 1", { |
| 1101 | /* Additional info available at Appendix A.7, |
| 1102 | * "VMX-Fixed Bits in CR0" */ |
| 1103 | { BITS_EOT } |
| 1104 | }}, |
| 1105 | {0x488, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR4_FIXED0", |
| 1106 | "Capability Reporting Register of CR4 Bits Fixed to 0", { |
| 1107 | /* Additional info available at Appendix A.8, |
| 1108 | * "VMX-Fixed Bits in CR4" */ |
| 1109 | { BITS_EOT } |
| 1110 | }}, |
| 1111 | {0x489, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR4_FIXED1", |
| 1112 | "Capability Reporting Register of CR4 Bits Fixed to 1", { |
| 1113 | /* Additional info available at Appendix A.8, |
| 1114 | * "VMX-Fixed Bits in CR4" */ |
| 1115 | { BITS_EOT } |
| 1116 | }}, |
| 1117 | {0x48a, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_VMCS_ENUM", |
| 1118 | "Capability Reporting Register of VMCS Field Enumeration", { |
| 1119 | /* Additional info available at Appendix A.9, |
| 1120 | * "VMCS Enumeration" */ |
| 1121 | { BITS_EOT } |
| 1122 | }}, |
| 1123 | {0x48b, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_PROCBASED_CTLS2", |
| 1124 | "Capability Reporting Register of Secondary \ |
| 1125 | Processor-based VM-execution Controls", { |
| 1126 | /* Additional info available at Appendix A.3, |
| 1127 | * "VM-Execution Controls" */ |
| 1128 | { BITS_EOT } |
| 1129 | }}, |
| 1130 | #endif |
| 1131 | {0x600, MSRTYPE_RDWR, MSR2(0,0), "IA32_DS_AREA", "DS Save Area", { |
| 1132 | /* Additional info available at Section 18.10.4 of Intel 64 |
| 1133 | * and IA-32 Architectures Software Developer's Manual, |
| 1134 | * "Debug Store (DS) Mechanism". |
| 1135 | */ |
| 1136 | { 63, 32, RESERVED }, // reserved if not in IA-32e mode |
| 1137 | { 31, 32, "Linear address of DS buffer management area", |
| 1138 | "R/W", PRESENT_HEX, { |
| 1139 | { BITVAL_EOT } |
| 1140 | }}, |
| 1141 | { BITS_EOT } |
| 1142 | }}, |
| 1143 | { MSR_EOT } |
| 1144 | }; |