Philipp Deppenwiese | d8fe443 | 2016-03-18 00:52:54 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #ifndef ME_H |
| 18 | #define ME_H |
| 19 | |
| 20 | #include <inttypes.h> |
| 21 | #include <pci/pci.h> |
| 22 | |
| 23 | #define ME_RETRY 100000 /* 1 second */ |
| 24 | #define ME_DELAY 10 /* 10 us */ |
| 25 | |
| 26 | #pragma pack(1) |
| 27 | |
| 28 | /* |
| 29 | * Management Engine PCI registers |
| 30 | */ |
| 31 | |
| 32 | #define PCI_ME_HFS 0x40 |
| 33 | #define ME_HFS_CWS_RESET 0 |
| 34 | #define ME_HFS_CWS_INIT 1 |
| 35 | #define ME_HFS_CWS_REC 2 |
| 36 | #define ME_HFS_CWS_NORMAL 5 |
| 37 | #define ME_HFS_CWS_WAIT 6 |
| 38 | #define ME_HFS_CWS_TRANS 7 |
| 39 | #define ME_HFS_CWS_INVALID 8 |
| 40 | #define ME_HFS_STATE_PREBOOT 0 |
| 41 | #define ME_HFS_STATE_M0_UMA 1 |
| 42 | #define ME_HFS_STATE_M3 4 |
| 43 | #define ME_HFS_STATE_M0 5 |
| 44 | #define ME_HFS_STATE_BRINGUP 6 |
| 45 | #define ME_HFS_STATE_ERROR 7 |
| 46 | #define ME_HFS_ERROR_NONE 0 |
| 47 | #define ME_HFS_ERROR_UNCAT 1 |
| 48 | #define ME_HFS_ERROR_IMAGE 3 |
| 49 | #define ME_HFS_ERROR_DEBUG 4 |
| 50 | #define ME_HFS_MODE_NORMAL 0 |
| 51 | #define ME_HFS_MODE_DEBUG 2 |
| 52 | #define ME_HFS_MODE_DIS 3 |
| 53 | #define ME_HFS_MODE_OVER_JMPR 4 |
| 54 | #define ME_HFS_MODE_OVER_MEI 5 |
| 55 | #define ME_HFS_BIOS_DRAM_ACK 1 |
| 56 | #define ME_HFS_ACK_NO_DID 0 |
| 57 | #define ME_HFS_ACK_RESET 1 |
| 58 | #define ME_HFS_ACK_PWR_CYCLE 2 |
| 59 | #define ME_HFS_ACK_S3 3 |
| 60 | #define ME_HFS_ACK_S4 4 |
| 61 | #define ME_HFS_ACK_S5 5 |
| 62 | #define ME_HFS_ACK_GBL_RESET 6 |
| 63 | #define ME_HFS_ACK_CONTINUE 7 |
| 64 | |
| 65 | struct me_hfs { |
| 66 | uint32_t working_state: 4; |
| 67 | uint32_t mfg_mode: 1; |
| 68 | uint32_t fpt_bad: 1; |
| 69 | uint32_t operation_state: 3; |
| 70 | uint32_t fw_init_complete: 1; |
| 71 | uint32_t ft_bup_ld_flr: 1; |
| 72 | uint32_t update_in_progress: 1; |
| 73 | uint32_t error_code: 4; |
| 74 | uint32_t operation_mode: 4; |
| 75 | uint32_t reserved: 4; |
| 76 | uint32_t boot_options_present: 1; |
| 77 | uint32_t ack_data: 3; |
| 78 | uint32_t bios_msg_ack: 4; |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 79 | } __attribute__((packed)); |
Philipp Deppenwiese | d8fe443 | 2016-03-18 00:52:54 +0100 | [diff] [blame] | 80 | |
| 81 | #define PCI_ME_UMA 0x44 |
| 82 | |
| 83 | struct me_uma { |
| 84 | uint32_t size: 6; |
| 85 | uint32_t reserved_1: 10; |
| 86 | uint32_t valid: 1; |
| 87 | uint32_t reserved_0: 14; |
| 88 | uint32_t set_to_one: 1; |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 89 | } __attribute__((packed)); |
Philipp Deppenwiese | d8fe443 | 2016-03-18 00:52:54 +0100 | [diff] [blame] | 90 | |
| 91 | #define PCI_ME_H_GS 0x4c |
| 92 | #define ME_INIT_DONE 1 |
| 93 | #define ME_INIT_STATUS_SUCCESS 0 |
| 94 | #define ME_INIT_STATUS_NOMEM 1 |
| 95 | #define ME_INIT_STATUS_ERROR 2 |
| 96 | |
| 97 | struct me_did { |
| 98 | uint32_t uma_base: 16; |
| 99 | uint32_t reserved: 8; |
| 100 | uint32_t status: 4; |
| 101 | uint32_t init_done: 4; |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 102 | } __attribute__((packed)); |
Philipp Deppenwiese | d8fe443 | 2016-03-18 00:52:54 +0100 | [diff] [blame] | 103 | |
| 104 | #define PCI_ME_GMES 0x48 |
| 105 | #define ME_GMES_PHASE_ROM 0 |
| 106 | #define ME_GMES_PHASE_BUP 1 |
| 107 | #define ME_GMES_PHASE_UKERNEL 2 |
| 108 | #define ME_GMES_PHASE_POLICY 3 |
| 109 | #define ME_GMES_PHASE_MODULE 4 |
| 110 | #define ME_GMES_PHASE_UNKNOWN 5 |
| 111 | #define ME_GMES_PHASE_HOST 6 |
| 112 | |
| 113 | struct me_gmes { |
| 114 | uint32_t bist_in_prog : 1; |
| 115 | uint32_t icc_prog_sts : 2; |
| 116 | uint32_t invoke_mebx : 1; |
| 117 | uint32_t cpu_replaced_sts : 1; |
| 118 | uint32_t mbp_rdy : 1; |
| 119 | uint32_t mfs_failure : 1; |
| 120 | uint32_t warm_rst_req_for_df : 1; |
| 121 | uint32_t cpu_replaced_valid : 1; |
| 122 | uint32_t reserved_1 : 2; |
| 123 | uint32_t fw_upd_ipu : 1; |
| 124 | uint32_t reserved_2 : 4; |
| 125 | uint32_t current_state: 8; |
| 126 | uint32_t current_pmevent: 4; |
| 127 | uint32_t progress_code: 4; |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 128 | } __attribute__((packed)); |
Philipp Deppenwiese | d8fe443 | 2016-03-18 00:52:54 +0100 | [diff] [blame] | 129 | |
| 130 | #define PCI_ME_HERES 0xbc |
| 131 | #define PCI_ME_EXT_SHA1 0x00 |
| 132 | #define PCI_ME_EXT_SHA256 0x02 |
| 133 | #define PCI_ME_HER(x) (0xc0+(4*(x))) |
| 134 | |
| 135 | struct me_heres { |
| 136 | uint32_t extend_reg_algorithm: 4; |
| 137 | uint32_t reserved: 26; |
| 138 | uint32_t extend_feature_present: 1; |
| 139 | uint32_t extend_reg_valid: 1; |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 140 | } __attribute__((packed)); |
Philipp Deppenwiese | d8fe443 | 2016-03-18 00:52:54 +0100 | [diff] [blame] | 141 | |
| 142 | struct me_thermal_reporting { |
| 143 | uint32_t polling_timeout: 8; |
| 144 | uint32_t smbus_ec_msglen: 8; |
| 145 | uint32_t smbus_ec_msgpec: 8; |
| 146 | uint32_t dimmnumber: 8; |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 147 | } __attribute__((packed)); |
Philipp Deppenwiese | d8fe443 | 2016-03-18 00:52:54 +0100 | [diff] [blame] | 148 | |
| 149 | /* |
| 150 | * Management Engine MEI registers |
| 151 | */ |
| 152 | |
| 153 | #define MEI_H_CB_WW 0x00 |
| 154 | #define MEI_H_CSR 0x04 |
| 155 | #define MEI_ME_CB_RW 0x08 |
| 156 | #define MEI_ME_CSR_HA 0x0c |
| 157 | |
| 158 | struct mei_csr { |
| 159 | uint32_t interrupt_enable: 1; |
| 160 | uint32_t interrupt_status: 1; |
| 161 | uint32_t interrupt_generate: 1; |
| 162 | uint32_t ready: 1; |
| 163 | uint32_t reset: 1; |
| 164 | uint32_t reserved: 3; |
| 165 | uint32_t buffer_read_ptr: 8; |
| 166 | uint32_t buffer_write_ptr: 8; |
| 167 | uint32_t buffer_depth: 8; |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 168 | } __attribute__((packed)); |
Philipp Deppenwiese | d8fe443 | 2016-03-18 00:52:54 +0100 | [diff] [blame] | 169 | |
| 170 | #define MEI_ADDRESS_HBM 0x00 |
| 171 | #define MEI_ADDRESS_CORE_WD 0x01 |
| 172 | #define MEI_ADDRESS_AMT 0x02 |
| 173 | #define MEI_ADDRESS_RESERVED 0x03 |
| 174 | #define MEI_ADDRESS_WDT 0x04 |
| 175 | #define MEI_ADDRESS_POLICY 0x05 |
| 176 | #define MEI_ADDRESS_PASSWORD 0x06 |
| 177 | #define MEI_ADDRESS_MKHI 0x07 |
| 178 | #define MEI_ADDRESS_ICC 0x08 |
| 179 | #define MEI_ADDRESS_THERMAL 0x09 |
| 180 | #define MEI_ADDRESS_SPI 0x0a |
| 181 | |
| 182 | #define MEI_HOST_ADDRESS 0 |
| 183 | |
| 184 | struct mei_header { |
| 185 | uint32_t client_address: 8; |
| 186 | uint32_t host_address: 8; |
| 187 | uint32_t length: 9; |
| 188 | uint32_t reserved: 6; |
| 189 | uint32_t is_complete: 1; |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 190 | } __attribute__((packed)); |
Philipp Deppenwiese | d8fe443 | 2016-03-18 00:52:54 +0100 | [diff] [blame] | 191 | |
| 192 | #define MKHI_GROUP_ID_CBM 0x00 |
| 193 | #define MKHI_GROUP_ID_PM 0x01 |
| 194 | #define MKHI_GROUP_ID_PWD 0x02 |
| 195 | #define MKHI_GROUP_ID_FWCAPS 0x03 |
| 196 | #define MKHI_GROUP_ID_APP 0x04 |
| 197 | #define MKHI_GROUP_ID_SPI 0x05 |
| 198 | #define MKHI_GROUP_ID_MDES 0x08 |
| 199 | #define MKHI_GROUP_ID_MAX 0x09 |
| 200 | #define MKHI_GROUP_ID_GEN 0xff |
| 201 | |
| 202 | #define MKHI_FWCAPS_GET_RULE 0x02 |
| 203 | #define MKHI_FWCAPS_SET_RULE 0x03 |
| 204 | #define MKHI_GLOBAL_RESET 0x0b |
| 205 | |
| 206 | #define GEN_GET_MKHI_VERSION 0x01 |
| 207 | #define GEN_GET_FW_VERSION 0x02 |
| 208 | #define GEN_UNCONFIG_NO_PWD 0x0d |
| 209 | #define GEN_SET_DEBUG_MEM 0x11 |
| 210 | |
| 211 | #define FWCAPS_ME_FWU_RULE 0x2e |
| 212 | #define FWCAPS_OVERRIDE 0x14 |
| 213 | |
| 214 | #define MKHI_THERMAL_REPORTING 0x00 |
| 215 | #define MKHI_GET_FW_VERSION 0x02 |
| 216 | #define MKHI_MDES_ENABLE 0x09 |
| 217 | #define MKHI_END_OF_POST 0x0c |
| 218 | #define MKHI_FEATURE_OVERRIDE 0x14 |
| 219 | |
| 220 | #define HBM_HOST_START_REQ_CMD 0x01 |
| 221 | #define HBM_HOST_STOP_REQ_CMD 0x02 |
| 222 | #define HBM_ME_STOP_REQ_CMD 0x03 |
| 223 | #define HBM_HOST_ENUM_REQ_CMD 0x04 |
| 224 | #define HBM_HOST_CLIENT_PROPERTIES_REQ_CMD 0x05 |
| 225 | #define HBM_CLIENT_CONNECT_REQ_CMD 0x06 |
| 226 | #define HBM_CLIENT_DISCONNECT_REQ_CMD 0x07 |
| 227 | |
| 228 | struct mkhi_header { |
| 229 | uint32_t group_id: 8; |
| 230 | uint32_t command: 7; |
| 231 | uint32_t is_response: 1; |
| 232 | uint32_t reserved: 8; |
| 233 | uint32_t result: 8; |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 234 | } __attribute__((packed)); |
Philipp Deppenwiese | d8fe443 | 2016-03-18 00:52:54 +0100 | [diff] [blame] | 235 | |
| 236 | struct me_fw_version { |
| 237 | uint16_t code_minor; |
| 238 | uint16_t code_major; |
| 239 | uint16_t code_build_number; |
| 240 | uint16_t code_hot_fix; |
| 241 | uint16_t recovery_minor; |
| 242 | uint16_t recovery_major; |
| 243 | uint16_t recovery_build_number; |
| 244 | uint16_t recovery_hot_fix; |
| 245 | uint16_t fitcminor; |
| 246 | uint16_t fitcmajor; |
| 247 | uint16_t fitcbuildno; |
| 248 | uint16_t fitchotfix; |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 249 | } __attribute__((packed)); |
Philipp Deppenwiese | d8fe443 | 2016-03-18 00:52:54 +0100 | [diff] [blame] | 250 | |
| 251 | |
| 252 | #define HECI_EOP_STATUS_SUCCESS 0x0 |
| 253 | #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1 |
| 254 | |
| 255 | #define CBM_RR_GLOBAL_RESET 0x01 |
| 256 | |
| 257 | #define GLOBAL_RESET_BIOS_MRC 0x01 |
| 258 | #define GLOBAL_RESET_BIOS_POST 0x02 |
| 259 | #define GLOBAL_RESET_MEBX 0x03 |
| 260 | |
| 261 | struct me_global_reset { |
| 262 | uint8_t request_origin; |
| 263 | uint8_t reset_type; |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 264 | } __attribute__((packed)); |
Philipp Deppenwiese | d8fe443 | 2016-03-18 00:52:54 +0100 | [diff] [blame] | 265 | |
| 266 | typedef enum { |
| 267 | ME_NORMAL_BIOS_PATH, |
| 268 | ME_S3WAKE_BIOS_PATH, |
| 269 | ME_ERROR_BIOS_PATH, |
| 270 | ME_RECOVERY_BIOS_PATH, |
| 271 | ME_DISABLE_BIOS_PATH, |
| 272 | ME_FIRMWARE_UPDATE_BIOS_PATH, |
| 273 | } me_bios_path; |
| 274 | |
| 275 | typedef struct { |
| 276 | uint32_t major_version : 16; |
| 277 | uint32_t minor_version : 16; |
| 278 | uint32_t hotfix_version : 16; |
| 279 | uint32_t build_version : 16; |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 280 | } __attribute__((packed)) mbp_fw_version_name; |
Philipp Deppenwiese | d8fe443 | 2016-03-18 00:52:54 +0100 | [diff] [blame] | 281 | |
| 282 | typedef struct { |
| 283 | uint8_t num_icc_profiles; |
| 284 | uint8_t icc_profile_soft_strap; |
| 285 | uint8_t icc_profile_index; |
| 286 | uint8_t reserved; |
| 287 | uint32_t register_lock_mask[3]; |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 288 | } __attribute__((packed)) mbp_icc_profile; |
Philipp Deppenwiese | d8fe443 | 2016-03-18 00:52:54 +0100 | [diff] [blame] | 289 | |
| 290 | typedef struct { |
| 291 | uint32_t full_net : 1; |
| 292 | uint32_t std_net : 1; |
| 293 | uint32_t manageability : 1; |
| 294 | uint32_t small_business : 1; |
| 295 | uint32_t l3manageability : 1; |
| 296 | uint32_t intel_at : 1; |
| 297 | uint32_t intel_cls : 1; |
| 298 | uint32_t reserved : 3; |
| 299 | uint32_t intel_mpc : 1; |
| 300 | uint32_t icc_over_clocking : 1; |
| 301 | uint32_t pavp : 1; |
| 302 | uint32_t reserved_1 : 4; |
| 303 | uint32_t ipv6 : 1; |
| 304 | uint32_t kvm : 1; |
| 305 | uint32_t och : 1; |
| 306 | uint32_t vlan : 1; |
| 307 | uint32_t tls : 1; |
| 308 | uint32_t reserved_4 : 1; |
| 309 | uint32_t wlan : 1; |
| 310 | uint32_t reserved_5 : 8; |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 311 | } __attribute__((packed)) mefwcaps_sku; |
Philipp Deppenwiese | d8fe443 | 2016-03-18 00:52:54 +0100 | [diff] [blame] | 312 | |
| 313 | typedef struct { |
| 314 | uint16_t lock_state : 1; |
| 315 | uint16_t authenticate_module : 1; |
| 316 | uint16_t s3authentication : 1; |
| 317 | uint16_t flash_wear_out : 1; |
| 318 | uint16_t flash_variable_security : 1; |
| 319 | uint16_t wwan3gpresent : 1; |
| 320 | uint16_t wwan3goob : 1; |
| 321 | uint16_t reserved : 9; |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 322 | } __attribute__((packed)) tdt_state_flag; |
Philipp Deppenwiese | d8fe443 | 2016-03-18 00:52:54 +0100 | [diff] [blame] | 323 | |
| 324 | typedef struct { |
| 325 | uint8_t state; |
| 326 | uint8_t last_theft_trigger; |
| 327 | tdt_state_flag flags; |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 328 | } __attribute__((packed)) tdt_state_info; |
Philipp Deppenwiese | d8fe443 | 2016-03-18 00:52:54 +0100 | [diff] [blame] | 329 | |
| 330 | typedef struct { |
| 331 | uint32_t platform_target_usage_type : 4; |
| 332 | uint32_t platform_target_market_type : 2; |
| 333 | uint32_t super_sku : 1; |
| 334 | uint32_t reserved : 1; |
| 335 | uint32_t intel_me_fw_image_type : 4; |
| 336 | uint32_t platform_brand : 4; |
| 337 | uint32_t reserved_1 : 16; |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 338 | } __attribute__((packed)) platform_type_rule_data; |
Philipp Deppenwiese | d8fe443 | 2016-03-18 00:52:54 +0100 | [diff] [blame] | 339 | |
| 340 | typedef struct { |
| 341 | mefwcaps_sku fw_capabilities; |
| 342 | uint8_t available; |
| 343 | } mbp_fw_caps; |
| 344 | |
| 345 | typedef struct { |
| 346 | uint16_t device_id; |
| 347 | uint16_t fuse_test_flags; |
| 348 | uint32_t umchid[4]; |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 349 | } __attribute__((packed)) mbp_rom_bist_data; |
Philipp Deppenwiese | d8fe443 | 2016-03-18 00:52:54 +0100 | [diff] [blame] | 350 | |
| 351 | typedef struct { |
| 352 | uint32_t key[8]; |
| 353 | } mbp_platform_key; |
| 354 | |
| 355 | typedef struct { |
| 356 | platform_type_rule_data rule_data; |
| 357 | uint8_t available; |
| 358 | } mbp_plat_type; |
| 359 | |
| 360 | typedef struct { |
| 361 | mbp_fw_version_name fw_version_name; |
| 362 | mbp_fw_caps fw_caps_sku; |
| 363 | mbp_rom_bist_data rom_bist_data; |
| 364 | mbp_platform_key platform_key; |
| 365 | mbp_plat_type fw_plat_type; |
| 366 | mbp_icc_profile icc_profile; |
| 367 | tdt_state_info at_state; |
| 368 | uint32_t mfsintegrity; |
| 369 | } me_bios_payload; |
| 370 | |
| 371 | typedef struct { |
| 372 | uint32_t mbp_size : 8; |
| 373 | uint32_t num_entries : 8; |
| 374 | uint32_t rsvd : 16; |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 375 | } __attribute__((packed)) mbp_header; |
Philipp Deppenwiese | d8fe443 | 2016-03-18 00:52:54 +0100 | [diff] [blame] | 376 | |
| 377 | typedef struct { |
| 378 | uint32_t app_id : 8; |
| 379 | uint32_t item_id : 8; |
| 380 | uint32_t length : 8; |
| 381 | uint32_t rsvd : 8; |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 382 | } __attribute__((packed)) mbp_item_header; |
Philipp Deppenwiese | d8fe443 | 2016-03-18 00:52:54 +0100 | [diff] [blame] | 383 | |
| 384 | struct me_fwcaps { |
| 385 | uint32_t id; |
| 386 | uint8_t length; |
| 387 | mefwcaps_sku caps_sku; |
| 388 | uint8_t reserved[3]; |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 389 | } __attribute__((packed)); |
Philipp Deppenwiese | d8fe443 | 2016-03-18 00:52:54 +0100 | [diff] [blame] | 390 | |
| 391 | struct me_debug_mem { |
| 392 | uint32_t debug_phys; |
| 393 | uint32_t debug_size; |
| 394 | uint32_t me_phys; |
| 395 | uint32_t me_size; |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame] | 396 | } __attribute__((packed)); |
Philipp Deppenwiese | d8fe443 | 2016-03-18 00:52:54 +0100 | [diff] [blame] | 397 | |
| 398 | void intel_me_status(uint32_t hfs, uint32_t gmes); |
| 399 | void mkhi_thermal(void); |
| 400 | uint32_t intel_mei_setup(struct pci_dev *dev); |
| 401 | void intel_mei_unmap(void); |
| 402 | int mkhi_get_fwcaps(void); |
Philipp Deppenwiese | 73add17 | 2016-08-26 02:10:51 +0200 | [diff] [blame] | 403 | int mkhi_get_fw_version(int *major, int *minor); |
Philipp Deppenwiese | d8fe443 | 2016-03-18 00:52:54 +0100 | [diff] [blame] | 404 | int mkhi_debug_me_memory(void *addr); |
| 405 | void mei_reset(void); |
| 406 | int intel_me_extend_valid(struct pci_dev *dev); |
| 407 | |
| 408 | #endif |