Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <arch/io.h> |
| 17 | #include <console/console.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 18 | #include <device/pci_def.h> |
| 19 | #include <delay.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 20 | #include <soc/spi.h> |
| 21 | #include <soc/rcba.h> |
| 22 | #include <soc/romstage.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 23 | |
| 24 | #define SPI_DELAY 10 /* 10us */ |
| 25 | #define SPI_RETRY 200000 /* 2s */ |
| 26 | |
| 27 | static int early_spi_read_block(u32 offset, u8 size, u8 *buffer) |
| 28 | { |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 29 | u32 *ptr32 = (u32 *)buffer; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 30 | u32 i; |
| 31 | |
| 32 | /* Clear status bits */ |
| 33 | SPIBAR16(SPIBAR_HSFS) |= SPIBAR_HSFS_AEL | SPIBAR_HSFS_FCERR | |
| 34 | SPIBAR_HSFS_FDONE; |
| 35 | |
| 36 | if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { |
| 37 | printk(BIOS_ERR, "SPI ERROR: transaction in progress\n"); |
| 38 | return -1; |
| 39 | } |
| 40 | |
| 41 | /* Set flash address */ |
| 42 | SPIBAR32(SPIBAR_FADDR) = offset; |
| 43 | |
| 44 | /* Setup read transaction */ |
| 45 | SPIBAR16(SPIBAR_HSFC) = SPIBAR_HSFC_BYTE_COUNT(size) | |
| 46 | SPIBAR_HSFC_CYCLE_READ; |
| 47 | |
Martin Roth | de7ed6f | 2014-12-07 14:58:18 -0700 | [diff] [blame] | 48 | /* Start transaction */ |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 49 | SPIBAR16(SPIBAR_HSFC) |= SPIBAR_HSFC_GO; |
| 50 | |
| 51 | /* Wait for completion */ |
| 52 | for (i = 0; i < SPI_RETRY; i++) { |
| 53 | if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { |
| 54 | /* Cycle in progress, wait 1ms */ |
| 55 | udelay(SPI_DELAY); |
| 56 | continue; |
| 57 | } |
| 58 | |
| 59 | if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_AEL) { |
| 60 | printk(BIOS_ERR, "SPI ERROR: Access Error\n"); |
| 61 | return -1; |
| 62 | |
| 63 | } |
| 64 | |
| 65 | if (SPIBAR16(SPIBAR_HSFS) & SPIBAR_HSFS_FCERR) { |
| 66 | printk(BIOS_ERR, "SPI ERROR: Flash Cycle Error\n"); |
| 67 | return -1; |
| 68 | } |
| 69 | break; |
| 70 | } |
| 71 | |
| 72 | if (i >= SPI_RETRY) { |
| 73 | printk(BIOS_ERR, "SPI ERROR: Timeout\n"); |
| 74 | return -1; |
| 75 | } |
| 76 | |
| 77 | /* Read the data */ |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 78 | for (i = 0; i < size; i += sizeof(u32)) { |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 79 | if (size-i >= 4) { |
| 80 | /* reading >= dword */ |
| 81 | *ptr32++ = SPIBAR32(SPIBAR_FDATA(i/sizeof(u32))); |
| 82 | } else { |
| 83 | /* reading < dword */ |
Lee Leahy | 26b7cd0 | 2017-03-16 18:47:55 -0700 | [diff] [blame] | 84 | u8 j, *ptr8 = (u8 *)ptr32; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 85 | u32 temp = SPIBAR32(SPIBAR_FDATA(i/sizeof(u32))); |
| 86 | for (j = 0; j < (size-i); j++) { |
| 87 | *ptr8++ = temp & 0xff; |
| 88 | temp >>= 8; |
| 89 | } |
| 90 | } |
| 91 | } |
| 92 | |
| 93 | return size; |
| 94 | } |
| 95 | |
| 96 | int early_spi_read(u32 offset, u32 size, u8 *buffer) |
| 97 | { |
| 98 | u32 current = 0; |
| 99 | |
| 100 | while (size > 0) { |
| 101 | u8 count = (size < 64) ? size : 64; |
| 102 | if (early_spi_read_block(offset + current, count, |
| 103 | buffer + current) < 0) |
| 104 | return -1; |
| 105 | size -= count; |
| 106 | current += count; |
| 107 | } |
| 108 | |
| 109 | return 0; |
| 110 | } |
| 111 | |
| 112 | /* |
| 113 | * Minimal set of commands to read WPSR from SPI. |
| 114 | * Don't use this code outside romstage -- it trashes the opmenu table. |
| 115 | * Returns 0 on success, < 0 on failure. |
| 116 | */ |
| 117 | int early_spi_read_wpsr(u8 *sr) |
| 118 | { |
| 119 | int retry; |
| 120 | |
| 121 | /* No address associated with rdsr */ |
| 122 | SPIBAR8(SPIBAR_OPTYPE) = 0x0; |
| 123 | /* Setup opcode[0] = read wpsr */ |
| 124 | SPIBAR8(SPIBAR_OPMENU_LOWER) = 0x5; |
| 125 | |
| 126 | /* Start transaction */ |
| 127 | SPIBAR16(SPIBAR_SSFC) = SPIBAR_SSFC_DATA | SPIBAR_SSFC_GO; |
| 128 | |
| 129 | /* Wait for error / complete status */ |
| 130 | for (retry = SPI_RETRY; retry; retry--) { |
| 131 | u16 status = SPIBAR16(SPIBAR_SSFS); |
| 132 | if (status & SPIBAR_SSFS_ERROR) { |
| 133 | printk(BIOS_ERR, "SPI rdsr failed\n"); |
| 134 | return -1; |
| 135 | } else if (status & SPIBAR_SSFS_DONE) { |
| 136 | break; |
| 137 | } |
| 138 | |
| 139 | udelay(SPI_DELAY); |
| 140 | } |
| 141 | |
| 142 | *sr = SPIBAR32(SPIBAR_FDATA(0)) & 0xff; |
| 143 | return 0; |
| 144 | } |