Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <arch/io.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 17 | #include <soc/gpio.h> |
| 18 | #include <soc/iomap.h> |
| 19 | #include <soc/lpc.h> |
| 20 | #include <soc/pci_devs.h> |
| 21 | #include <soc/romstage.h> |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 22 | |
| 23 | void byt_config_com1_and_enable(void) |
| 24 | { |
| 25 | uint32_t reg; |
| 26 | |
| 27 | /* Enable the UART hardware for COM1. */ |
| 28 | reg = 1; |
| 29 | pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); |
| 30 | |
Shawn Nematbakhsh | 3b036f7 | 2013-10-08 11:31:21 -0700 | [diff] [blame] | 31 | /* Set up the pads to select the UART function */ |
| 32 | score_select_func(UART_RXD_PAD, 1); |
| 33 | score_select_func(UART_TXD_PAD, 1); |
Aaron Durbin | 9a7d7bc | 2013-09-07 00:41:48 -0500 | [diff] [blame] | 34 | } |