Aaron Durbin | fd039f7 | 2013-10-04 11:11:52 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Aaron Durbin | fd039f7 | 2013-10-04 11:11:52 -0500 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <stddef.h> |
| 17 | #include <arch/io.h> |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 18 | #include <console/console.h> |
| 19 | #include <device/device.h> |
| 20 | #include <device/pci_def.h> |
Julius Werner | 18ea2d3 | 2014-10-07 16:42:17 -0700 | [diff] [blame] | 21 | #include <soc/iomap.h> |
| 22 | #include <soc/iosf.h> |
| 23 | #include <soc/lpc.h> |
| 24 | #include <soc/pci_devs.h> |
| 25 | #include <soc/pmc.h> |
| 26 | #include <soc/romstage.h> |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 27 | #include "../chip.h" |
Aaron Durbin | fd039f7 | 2013-10-04 11:11:52 -0500 | [diff] [blame] | 28 | |
| 29 | void tco_disable(void) |
| 30 | { |
| 31 | uint32_t reg; |
| 32 | |
| 33 | reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); |
| 34 | reg |= TCO_TMR_HALT; |
| 35 | outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); |
| 36 | } |
Aaron Durbin | 189aa3e | 2013-10-04 11:17:45 -0500 | [diff] [blame] | 37 | |
| 38 | /* This sequence signals the PUNIT to start running. */ |
| 39 | void punit_init(void) |
| 40 | { |
| 41 | uint32_t reg; |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 42 | uint8_t rid; |
| 43 | const struct device *dev; |
| 44 | const struct soc_intel_baytrail_config *cfg = NULL; |
Aaron Durbin | 189aa3e | 2013-10-04 11:17:45 -0500 | [diff] [blame] | 45 | |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 46 | rid = pci_read_config8(IOSF_PCI_DEV, REVID); |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 47 | dev = pcidev_on_root(SOC_DEV, SOC_FUNC); |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 48 | |
| 49 | if (dev) |
| 50 | cfg = dev->chip_info; |
| 51 | |
| 52 | reg = iosf_punit_read(SB_BIOS_CONFIG); |
Aaron Durbin | 189aa3e | 2013-10-04 11:17:45 -0500 | [diff] [blame] | 53 | /* Write bits 17:16 of SB_BIOS_CONFIG in the PUNIT. */ |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 54 | reg |= SB_BIOS_CONFIG_PERF_MODE | SB_BIOS_CONFIG_PDM_MODE; |
| 55 | /* Configure VR low power mode for C0 and above. */ |
| 56 | if (rid >= RID_C_STEPPING_START && cfg != NULL && |
| 57 | (cfg->vnn_ps2_enable || cfg->vcc_ps2_enable)) { |
Paul Menzel | 63ebb5b | 2018-09-06 09:05:25 +0200 | [diff] [blame] | 58 | printk(BIOS_DEBUG, "Enabling VR PS2 mode:"); |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 59 | if (cfg->vnn_ps2_enable) { |
| 60 | reg |= SB_BIOS_CONFIG_PS2_EN_VNN; |
Paul Menzel | 63ebb5b | 2018-09-06 09:05:25 +0200 | [diff] [blame] | 61 | printk(BIOS_DEBUG, " VNN"); |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 62 | } |
| 63 | if (cfg->vcc_ps2_enable) { |
| 64 | reg |= SB_BIOS_CONFIG_PS2_EN_VCC; |
Paul Menzel | 63ebb5b | 2018-09-06 09:05:25 +0200 | [diff] [blame] | 65 | printk(BIOS_DEBUG, " VCC"); |
Shawn Nematbakhsh | 51d787a | 2014-01-16 17:52:21 -0800 | [diff] [blame] | 66 | } |
| 67 | printk(BIOS_DEBUG, "\n"); |
| 68 | } |
| 69 | iosf_punit_write(SB_BIOS_CONFIG, reg); |
Aaron Durbin | 189aa3e | 2013-10-04 11:17:45 -0500 | [diff] [blame] | 70 | |
| 71 | /* Write bits 1:0 of BIOS_RESET_CPL in the PUNIT. */ |
| 72 | reg = BIOS_RESET_CPL_ALL_DONE | BIOS_RESET_CPL_RESET_DONE; |
| 73 | pci_write_config32(IOSF_PCI_DEV, MDR_REG, reg); |
| 74 | reg = IOSF_OPCODE(IOSF_OP_WRITE_PMC) | IOSF_PORT(IOSF_PORT_PMC) | |
| 75 | IOSF_REG(BIOS_RESET_CPL) | IOSF_BYTE_EN_0; |
| 76 | pci_write_config32(IOSF_PCI_DEV, MCR_REG, reg); |
| 77 | } |