| Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
| Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3 | |
| Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 4 | #include "ironlake.h" |
| Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 5 | |
| 6 | #define PCI_DEV_SNB PCI_DEV(0, 0, 0) |
| 7 | |
| Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 8 | void intel_ironlake_finalize_smm(void) |
| Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 9 | { |
| Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 10 | MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ |
| 11 | MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ |
| 12 | MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */ |
| 13 | MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */ |
| 14 | MCHBAR32_OR(0x6800, 1 << 31); |
| 15 | MCHBAR32_OR(0x7000, 1 << 31); |
| 16 | MCHBAR32_OR(0x77fc, 1 << 0); |
| 17 | |
| 18 | /* Memory Controller Lockdown */ |
| 19 | MCHBAR8(0x50fc) = 0x8f; |
| 20 | |
| 21 | /* Read+write the following */ |
| 22 | MCHBAR32(0x6030) = MCHBAR32(0x6030); |
| 23 | MCHBAR32(0x6034) = MCHBAR32(0x6034); |
| 24 | MCHBAR32(0x6008) = MCHBAR32(0x6008); |
| 25 | } |