| Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
| Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 3 | |
| Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 4 | #ifndef NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H |
| 5 | #define NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H |
| Iru Cai | d7ee9dd | 2016-02-24 15:03:58 +0800 | [diff] [blame] | 6 | |
| Vladimir Serbinenko | a71bdc3 | 2014-08-30 00:35:39 +0200 | [diff] [blame] | 7 | #include <drivers/intel/gma/i915.h> |
| 8 | |
| Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 9 | /* |
| 10 | * Digital Port Hotplug Enable: |
| 11 | * 0x04 = Enabled, 2ms short pulse |
| 12 | * 0x05 = Enabled, 4.5ms short pulse |
| 13 | * 0x06 = Enabled, 6ms short pulse |
| 14 | * 0x07 = Enabled, 100ms short pulse |
| 15 | */ |
| Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 16 | struct northbridge_intel_ironlake_config { |
| Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 17 | u8 gpu_dp_b_hotplug; /* Digital Port B Hotplug Config */ |
| 18 | u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ |
| 19 | u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */ |
| 20 | |
| 21 | u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */ |
| 22 | u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ |
| 23 | u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ |
| 24 | u16 gpu_panel_power_down_delay; /* T3 time sequence */ |
| 25 | u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ |
| 26 | u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ |
| 27 | |
| 28 | u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ |
| 29 | u32 gpu_pch_backlight; /* PCH Backlight PWM value */ |
| Vladimir Serbinenko | 1315730 | 2014-02-19 22:18:08 +0100 | [diff] [blame] | 30 | |
| Vladimir Serbinenko | a71bdc3 | 2014-08-30 00:35:39 +0200 | [diff] [blame] | 31 | struct i915_gpu_controller_info gfx; |
| Patrick Rudolph | 266a1f7 | 2016-06-09 18:13:34 +0200 | [diff] [blame] | 32 | |
| 33 | /* |
| 34 | * Maximum PCI mmio size in MiB. |
| 35 | */ |
| 36 | u16 pci_mmio_size; |
| Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 37 | }; |
| Iru Cai | d7ee9dd | 2016-02-24 15:03:58 +0800 | [diff] [blame] | 38 | |
| Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 39 | #endif /* NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H */ |