blob: 270ad90c32845335c69a0026b64eded590c4332c [file] [log] [blame]
Angel Pons4b429832020-04-02 23:48:50 +02001/* SPDX-License-Identifier: GPL-2.0-only */
2/* This file is part of the coreboot project. */
Patrick Georgi2efc8802012-11-06 11:03:53 +01003
4#include "hostbridge.asl"
5#include "../gm45.h"
Elyes HAOUAS4ec67fc2019-10-30 12:39:17 +01006#include <southbridge/intel/common/rcba.h>
Patrick Georgi2efc8802012-11-06 11:03:53 +01007
8/* PCI Device Resource Consumption */
9Device (PDRC)
10{
11 Name (_HID, EISAID("PNP0C02"))
12 Name (_UID, 1)
13
14 // This does not seem to work correctly yet - set values statically for
15 // now.
16
17 //Name (PDRS, ResourceTemplate() {
18 // Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, RCRB) // RCBA
19 // Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR
20 // Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR
21 // Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR
22 // Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, PCIE) // PCIE BAR
23 // Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH
24 //})
25
26 Name (PDRS, ResourceTemplate() {
Elyes HAOUAS4ec67fc2019-10-30 12:39:17 +010027 Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000)
Patrick Georgi2efc8802012-11-06 11:03:53 +010028 Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
29 Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000)
30 Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000)
Kyösti Mälkki503d3242019-03-05 07:54:28 +020031 Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x04000000)
Patrick Georgi2efc8802012-11-06 11:03:53 +010032 Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
33 Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
34 Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
35 })
36
37 // Current Resource Settings
38 Method (_CRS, 0, Serialized)
39 {
40 //CreateDwordField(PDRS, ^RCRB._BAS, RBR0)
41 //ShiftLeft(\_SB.PCI0.LPCB.RCBA, 14, RBR0)
42
43 //CreateDwordField(PDRS, ^MCHB._BAS, MBR0)
44 //ShiftLeft(\_SB.PCI0.MCHC.MHBR, 14, MBR0)
45
46 //CreateDwordField(PDRS, ^DMIB._BAS, DBR0)
47 //ShiftLeft(\_SB.PCI0.MCHC.DMBR, 12, DBR0)
48
49 //CreateDwordField(PDRS, ^EGPB._BAS, EBR0)
50 //ShiftLeft(\_SB.PCI0.MCHC.EPBR, 12, EBR0)
51
52 //CreateDwordField(PDRS, ^PCIE._BAS, PBR0)
53 //ShiftLeft(\_SB.PCI0.MCHC.PXBR, 26, PBR0)
54
55 //CreateDwordField(PDRS, ^PCIE._LEN, PSZ0)
56 //ShiftLeft(0x10000000, \_SB.PCI0.MCHC.PXSZ, PSZ0)
57
58 Return(PDRS)
59 }
60}
61
62// PCIe graphics port 0:1.0
63#include "peg.asl"