| Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 1 | config SOC_NVIDIA_TEGRA210 |
| 2 | bool |
| 3 | default n |
| 4 | select ARCH_BOOTBLOCK_ARMV4 |
| Julius Werner | 86fc11d | 2015-10-09 13:37:58 -0700 | [diff] [blame] | 5 | select BOOTBLOCK_CUSTOM |
| Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 6 | select ARCH_VERSTAGE_ARMV4 |
| 7 | select ARCH_ROMSTAGE_ARMV4 |
| 8 | select ARCH_RAMSTAGE_ARMV8_64 |
| Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 9 | select BOOTBLOCK_CONSOLE |
| 10 | select GIC |
| 11 | select HAVE_MONOTONIC_TIMER |
| 12 | select GENERIC_UDELAY |
| 13 | select HAVE_HARD_RESET |
| 14 | select HAVE_UART_SPECIAL |
| Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 15 | select ARM64_USE_ARM_TRUSTED_FIRMWARE |
| 16 | select HAS_PRECBMEM_TIMESTAMP_REGION |
| Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 17 | select GENERIC_GPIO_LIB |
| 18 | |
| 19 | if SOC_NVIDIA_TEGRA210 |
| 20 | |
| Martin Roth | 967cd9a | 2015-08-18 14:22:58 -0600 | [diff] [blame] | 21 | config CHROMEOS |
| 22 | select CHROMEOS_RAMOOPS_NON_ACPI |
| 23 | |
| Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 24 | config MAINBOARD_DO_DSI_INIT |
| 25 | bool "Use dsi graphics interface" |
| 26 | depends on MAINBOARD_DO_NATIVE_VGA_INIT |
| 27 | default n |
| 28 | help |
| 29 | Initialize dsi display |
| 30 | |
| 31 | config MAINBOARD_DO_SOR_INIT |
| 32 | bool "Use dp graphics interface" |
| 33 | depends on MAINBOARD_DO_NATIVE_VGA_INIT |
| 34 | default n |
| 35 | help |
| 36 | Initialize dp display |
| 37 | |
| Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 38 | choice CONSOLE_SERIAL_TEGRA210_UART_CHOICES |
| 39 | prompt "Serial Console UART" |
| 40 | default CONSOLE_SERIAL_TEGRA210_UARTA |
| Martin Roth | df02c33 | 2015-07-01 23:09:42 -0600 | [diff] [blame] | 41 | depends on CONSOLE_SERIAL |
| Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 42 | |
| 43 | config CONSOLE_SERIAL_TEGRA210_UARTA |
| 44 | bool "UARTA" |
| 45 | help |
| 46 | Serial console on UART A. |
| 47 | |
| 48 | config CONSOLE_SERIAL_TEGRA210_UARTB |
| 49 | bool "UARTB" |
| 50 | help |
| 51 | Serial console on UART B. |
| 52 | |
| 53 | config CONSOLE_SERIAL_TEGRA210_UARTC |
| 54 | bool "UARTC" |
| 55 | help |
| 56 | Serial console on UART C. |
| 57 | |
| 58 | config CONSOLE_SERIAL_TEGRA210_UARTD |
| 59 | bool "UARTD" |
| 60 | help |
| 61 | Serial console on UART D. |
| 62 | |
| 63 | config CONSOLE_SERIAL_TEGRA210_UARTE |
| 64 | bool "UARTE" |
| 65 | help |
| 66 | Serial console on UART E. |
| 67 | |
| 68 | endchoice |
| 69 | |
| 70 | config CONSOLE_SERIAL_TEGRA210_UART_ADDRESS |
| 71 | hex |
| Martin Roth | df02c33 | 2015-07-01 23:09:42 -0600 | [diff] [blame] | 72 | depends on CONSOLE_SERIAL |
| Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 73 | default 0x70006000 if CONSOLE_SERIAL_TEGRA210_UARTA |
| 74 | default 0x70006040 if CONSOLE_SERIAL_TEGRA210_UARTB |
| 75 | default 0x70006200 if CONSOLE_SERIAL_TEGRA210_UARTC |
| 76 | default 0x70006300 if CONSOLE_SERIAL_TEGRA210_UARTD |
| 77 | default 0x70006400 if CONSOLE_SERIAL_TEGRA210_UARTE |
| 78 | help |
| 79 | Map the UART names to the respective MMIO addres. |
| 80 | |
| 81 | config BOOTROM_SDRAM_INIT |
| 82 | bool "SoC BootROM does SDRAM init with full BCT" |
| 83 | default n |
| 84 | help |
| 85 | Use during Foster LPDDR4 bringup. |
| 86 | |
| 87 | config TRUSTZONE_CARVEOUT_SIZE_MB |
| 88 | hex "Size of Trust Zone region" |
| 89 | default 0x14 |
| 90 | help |
| 91 | Size of Trust Zone area in MiB to reserve in memory map. |
| 92 | |
| Furquan Shaikh | 3ae5044 | 2015-07-07 21:35:56 -0700 | [diff] [blame] | 93 | config TTB_SIZE_MB |
| 94 | hex "Size of TTB" |
| 95 | default 0x4 |
| 96 | help |
| 97 | Maximum size of Translation Table Buffer in MiB. |
| 98 | |
| 99 | config SEC_COMPONENT_SIZE_MB |
| 100 | hex "Size of resident EL3 components" |
| 101 | default 0x10 |
| 102 | help |
| 103 | Maximum size of resident EL3 components in MiB including BL31 and |
| 104 | Secure OS. |
| 105 | |
| Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 106 | # Default to 700MHz. This value is based on nv bootloader setting. |
| 107 | config PLLX_KHZ |
| Martin Roth | 45895f1 | 2015-07-01 19:38:29 -0600 | [diff] [blame] | 108 | int |
| 109 | default 700000 |
| Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 110 | |
| 111 | config HAVE_MTC |
| 112 | bool "Add external Memory controller Training Code binary" |
| 113 | default n |
| 114 | depends on USE_BLOBS |
| 115 | help |
| 116 | Select this option to add emc training firmware |
| 117 | |
| 118 | if HAVE_MTC |
| 119 | |
| 120 | config MTC_FILE |
| 121 | string "tegra mtc firmware filename" |
| 122 | default "tegra_mtc.bin" |
| 123 | help |
| 124 | The filename of the mtc firmware |
| 125 | |
| 126 | config MTC_DIRECTORY |
| 127 | string "Directory where MTC firmware file is located" |
| 128 | default "." |
| 129 | help |
| 130 | Path to directory where MTC firmware file is located. |
| 131 | |
| 132 | config MTC_ADDRESS |
| 133 | hex |
| 134 | default 0x81000000 |
| 135 | help |
| 136 | The DRAM location where MTC firmware to be loaded in. This location |
| 137 | needs to be consistent with the location defined in tegra_mtc.ld |
| 138 | |
| 139 | endif # HAVE_MTC |
| 140 | |
| Vladimir Serbinenko | 5226266 | 2015-10-11 02:17:21 +0200 | [diff] [blame] | 141 | endif # SOC_NVIDIA_TEGRA210 |