Iru Cai | 928c6c6 | 2017-06-15 18:18:51 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
Elyes HAOUAS | 4ad1446 | 2018-06-16 18:29:33 +0200 | [diff] [blame^] | 17 | #include <northbridge/intel/sandybridge/raminit_native.h> |
Iru Cai | 928c6c6 | 2017-06-15 18:18:51 +0800 | [diff] [blame] | 18 | #include <superio/nuvoton/nct6776/nct6776.h> |
| 19 | #include <superio/nuvoton/common/nuvoton.h> |
| 20 | |
| 21 | #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) |
| 22 | |
| 23 | void pch_enable_lpc(void) |
| 24 | { |
| 25 | pci_write_config16(PCH_LPC_DEV, LPC_EN, |
| 26 | CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); |
| 27 | pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0000); |
| 28 | } |
| 29 | |
Nico Huber | ff4025c | 2018-01-14 12:34:43 +0100 | [diff] [blame] | 30 | void mainboard_rcba_config(void) |
Iru Cai | 928c6c6 | 2017-06-15 18:18:51 +0800 | [diff] [blame] | 31 | { |
Iru Cai | 928c6c6 | 2017-06-15 18:18:51 +0800 | [diff] [blame] | 32 | } |
| 33 | |
| 34 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 35 | { 1, 0, 0 }, |
| 36 | { 1, 0, 0 }, |
| 37 | { 1, 1, 1 }, |
| 38 | { 1, 1, 1 }, |
| 39 | { 1, 1, 2 }, |
| 40 | { 1, 1, 2 }, |
| 41 | { 1, 0, 3 }, |
| 42 | { 1, 0, 3 }, |
| 43 | { 1, 0, 4 }, |
| 44 | { 1, 0, 4 }, |
| 45 | { 1, 0, 6 }, |
| 46 | { 1, 1, 5 }, |
| 47 | { 1, 1, 5 }, |
| 48 | { 1, 0, 6 }, |
| 49 | }; |
| 50 | |
| 51 | void mainboard_early_init(int s3resume) |
| 52 | { |
| 53 | } |
| 54 | |
| 55 | void mainboard_config_superio(void) |
| 56 | { |
| 57 | /* Set GPIOs on superio, enable UART */ |
| 58 | nuvoton_pnp_enter_conf_state(SERIAL_DEV); |
| 59 | pnp_set_logical_device(SERIAL_DEV); |
| 60 | |
| 61 | pnp_write_config(SERIAL_DEV, 0x1c, 0x80); |
| 62 | pnp_write_config(SERIAL_DEV, 0x27, 0x80); |
| 63 | pnp_write_config(SERIAL_DEV, 0x2a, 0x60); |
| 64 | |
| 65 | nuvoton_pnp_exit_conf_state(SERIAL_DEV); |
| 66 | |
| 67 | nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
| 68 | } |
| 69 | |
| 70 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
| 71 | { |
| 72 | read_spd(&spd[0], 0x50, id_only); |
| 73 | read_spd(&spd[1], 0x51, id_only); |
| 74 | read_spd(&spd[2], 0x52, id_only); |
| 75 | read_spd(&spd[3], 0x53, id_only); |
| 76 | } |