Angel Pons | e67ab18 | 2020-04-04 18:51:11 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 2 | #include <assert.h> |
| 3 | #include <console/console.h> |
| 4 | #include <delay.h> |
Biao Huang | 0dd8315 | 2015-09-03 17:39:12 +0800 | [diff] [blame] | 5 | #include <soc/addressmap.h> |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 6 | #include <soc/mt6391.h> |
| 7 | #include <soc/pmic_wrap.h> |
Biao Huang | 0dd8315 | 2015-09-03 17:39:12 +0800 | [diff] [blame] | 8 | #include <types.h> |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 9 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 10 | #if CONFIG(DEBUG_PMIC) |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 11 | #define DEBUG_PMIC(level, x...) printk(level, x) |
| 12 | #else |
| 13 | #define DEBUG_PMIC(level, x...) |
| 14 | #endif |
| 15 | |
Yidi Lin | a622f28 | 2016-01-29 17:25:03 +0800 | [diff] [blame] | 16 | int mt6391_configure_ca53_voltage(int uv) |
| 17 | { |
| 18 | /* target voltage = 700mv + 6.25mv * buck_val */ |
| 19 | u16 buck_val = (uv - 700000) / 6250; |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 20 | u16 current_val = pwrap_read_field(PMIC_RG_VCA15_CON12, 0x7f, 0x0); |
Yidi Lin | a622f28 | 2016-01-29 17:25:03 +0800 | [diff] [blame] | 21 | |
| 22 | assert(buck_val < (1 << 8)); |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 23 | pwrap_write_field(PMIC_RG_VCA15_CON9, buck_val, 0x7f, 0x0); |
| 24 | pwrap_write_field(PMIC_RG_VCA15_CON10, buck_val, 0x7f, 0x0); |
Yidi Lin | a622f28 | 2016-01-29 17:25:03 +0800 | [diff] [blame] | 25 | |
| 26 | /* For buck delay, default slew rate is 6.25mv/0.5us */ |
| 27 | if (buck_val > current_val) |
Elyes Haouas | 4abc5c5 | 2023-08-13 12:50:46 +0200 | [diff] [blame^] | 28 | return ((buck_val - current_val) / 2); |
Yidi Lin | a622f28 | 2016-01-29 17:25:03 +0800 | [diff] [blame] | 29 | else |
| 30 | return 0; |
| 31 | } |
| 32 | |
Koro Chen | 64a6b92 | 2015-07-31 17:11:04 +0800 | [diff] [blame] | 33 | static void mt6391_configure_vcama(enum ldo_voltage vsel) |
| 34 | { |
| 35 | /* 2'b00: 1.5V |
| 36 | * 2'b01: 1.8V |
| 37 | * 2'b10: 2.5V |
| 38 | * 2'b11: 2.8V |
| 39 | */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 40 | pwrap_write_field(PMIC_RG_ANALDO_CON6, vsel - 2, |
| 41 | PMIC_RG_VCAMA_VOSEL_MASK, PMIC_RG_VCAMA_VOSEL_SHIFT); |
| 42 | pwrap_write_field(PMIC_RG_ANALDO_CON2, 1, |
| 43 | PMIC_RG_VCAMA_EN_MASK, PMIC_RG_VCAMA_EN_SHIFT); |
Koro Chen | 64a6b92 | 2015-07-31 17:11:04 +0800 | [diff] [blame] | 44 | } |
| 45 | |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 46 | void mt6391_configure_ldo(enum ldo_power ldo, enum ldo_voltage vsel) |
| 47 | { |
| 48 | u16 addr; |
| 49 | switch (ldo) { |
| 50 | case LDO_VCAMD: |
| 51 | assert(vsel != 0); |
| 52 | if (vsel == LDO_1P22) |
| 53 | vsel = 0; |
| 54 | break; |
Jitao Shi | 8ea218b | 2016-01-11 19:24:37 +0800 | [diff] [blame] | 55 | case LDO_VGP2: |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 56 | assert(vsel != 1); |
| 57 | if (vsel == LDO_1P0) |
| 58 | vsel = 1; |
| 59 | break; |
| 60 | case LDO_VGP5: |
| 61 | assert(vsel != 7); |
| 62 | if (vsel == LDO_2P0) |
| 63 | vsel = 7; |
| 64 | break; |
Koro Chen | 64a6b92 | 2015-07-31 17:11:04 +0800 | [diff] [blame] | 65 | case LDO_VCAMA: |
| 66 | assert(vsel > LDO_1P3 && vsel < LDO_3P0); |
| 67 | mt6391_configure_vcama(vsel); |
| 68 | return; |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 69 | default: |
| 70 | break; |
| 71 | } |
| 72 | assert(vsel < LDO_NUM_VOLTAGES); |
| 73 | |
| 74 | if (ldo == LDO_VGP6) |
| 75 | addr = PMIC_RG_DIGLDO_CON33; |
| 76 | else |
| 77 | addr = PMIC_RG_DIGLDO_CON19 + ldo * 2; |
| 78 | |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 79 | pwrap_write_field(addr, vsel, 0x7, 5); |
| 80 | pwrap_write_field(PMIC_RG_DIGLDO_CON5 + ldo * 2, 1, 1, 15); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 81 | |
| 82 | } |
| 83 | |
| 84 | void mt6391_enable_reset_when_ap_resets(void) |
| 85 | { |
| 86 | /* Enable AP watchdog reset */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 87 | pwrap_write_field(PMIC_RG_TOP_RST_MISC, 0x0, 0x1, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 88 | } |
| 89 | |
| 90 | static void mt6391_init_setting(void) |
| 91 | { |
| 92 | /* Enable PMIC RST function (depends on main chip RST function) */ |
| 93 | /* |
| 94 | * state1: RG_SYSRSTB_EN = 1, RG_STRUP_MAN_RST_EN=1, RG_RST_PART_SEL=1 |
| 95 | * state2: RG_SYSRSTB_EN = 1, RG_STRUP_MAN_RST_EN=0, RG_RST_PART_SEL=1 |
| 96 | * state3: RG_SYSRSTB_EN = 1, RG_STRUP_MAN_RST_EN=x, RG_RST_PART_SEL=0 |
| 97 | */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 98 | pwrap_write_field(PMIC_RG_TOP_RST_MISC, 0x1, 0x1, 1); |
| 99 | pwrap_write_field(PMIC_RG_TOP_RST_MISC, 0x0, 0x1, 2); |
| 100 | pwrap_write_field(PMIC_RG_TOP_RST_MISC, 0x1, 0x1, 4); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 101 | |
| 102 | /* Disable AP watchdog reset */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 103 | pwrap_write_field(PMIC_RG_TOP_RST_MISC, 0x1, 0x1, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 104 | |
| 105 | /* Enable CA15 by default for different PMIC behavior */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 106 | pwrap_write_field(PMIC_RG_VCA15_CON7, 0x1, 0x1, 0); |
| 107 | pwrap_write_field(PMIC_RG_VSRMCA15_CON7, 0x1, 0x1, 0); |
| 108 | pwrap_write_field(PMIC_RG_VPCA7_CON7, 0x1, 0x1, 0); |
Tristan Shieh | f42db11 | 2018-06-06 12:52:20 +0800 | [diff] [blame] | 109 | udelay(200); /* delay for Buck ready */ |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 110 | |
| 111 | /* [3:3]: RG_PWMOC_CK_PDN; For OC protection */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 112 | pwrap_write_field(PMIC_RG_TOP_CKPDN, 0x0, 0x1, 3); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 113 | /* [9:9]: RG_SRCVOLT_HW_AUTO_EN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 114 | pwrap_write_field(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 9); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 115 | /* [8:8]: RG_OSC_SEL_AUTO; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 116 | pwrap_write_field(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 8); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 117 | /* [6:6]: RG_SMPS_DIV2_SRC_AUTOFF_DIS; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 118 | pwrap_write_field(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 6); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 119 | /* [5:5]: RG_SMPS_AUTOFF_DIS; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 120 | pwrap_write_field(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 5); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 121 | /* [7:7]: VDRM_DEG_EN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 122 | pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 7); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 123 | /* [6:6]: VSRMCA7_DEG_EN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 124 | pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 6); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 125 | /* [5:5]: VPCA7_DEG_EN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 126 | pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 5); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 127 | /* [4:4]: VIO18_DEG_EN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 128 | pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 4); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 129 | /* [3:3]: VGPU_DEG_EN; For OC protection */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 130 | pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 3); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 131 | /* [2:2]: VCORE_DEG_EN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 132 | pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 2); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 133 | /* [1:1]: VSRMCA15_DEG_EN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 134 | pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 1); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 135 | /* [0:0]: VCA15_DEG_EN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 136 | pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 137 | /* [11:11]: RG_INT_EN_THR_H; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 138 | pwrap_write_field(PMIC_RG_INT_CON0, 0x1, 0x1, 11); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 139 | /* [10:10]: RG_INT_EN_THR_L; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 140 | pwrap_write_field(PMIC_RG_INT_CON0, 0x1, 0x1, 10); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 141 | /* [4:4]: RG_INT_EN_BAT_L; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 142 | pwrap_write_field(PMIC_RG_INT_CON0, 0x1, 0x1, 4); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 143 | /* [11:11]: RG_INT_EN_VGPU; OC protection */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 144 | pwrap_write_field(PMIC_RG_INT_CON1, 0x1, 0x1, 11); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 145 | /* [8:8]: RG_INT_EN_VCA15; OC protection */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 146 | pwrap_write_field(PMIC_RG_INT_CON1, 0x1, 0x1, 8); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 147 | /* [12:0]: BUCK_RSV; for OC protection */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 148 | pwrap_write_field(PMIC_RG_BUCK_CON3, 0x600, 0x0FFF, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 149 | /* [11:10]: QI_VCORE_VSLEEP; sleep mode only (0.7V) */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 150 | pwrap_write_field(PMIC_RG_BUCK_CON8, 0x0, 0x3, 10); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 151 | /* [7:6]: QI_VSRMCA7_VSLEEP; sleep mode only (0.85V) */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 152 | pwrap_write_field(PMIC_RG_BUCK_CON8, 0x0, 0x3, 6); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 153 | /* [5:4]: QI_VSRMCA15_VSLEEP; sleep mode only (0.7V) */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 154 | pwrap_write_field(PMIC_RG_BUCK_CON8, 0x1, 0x3, 4); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 155 | /* [3:2]: QI_VPCA7_VSLEEP; sleep mode only (0.85V) */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 156 | pwrap_write_field(PMIC_RG_BUCK_CON8, 0x0, 0x3, 2); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 157 | /* [1:0]: QI_VCA15_VSLEEP; sleep mode only (0.7V) */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 158 | pwrap_write_field(PMIC_RG_BUCK_CON8, 0x1, 0x3, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 159 | /* [13:12]: RG_VCA15_CSL2; for OC protection */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 160 | pwrap_write_field(PMIC_RG_VCA15_CON1, 0x0, 0x3, 12); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 161 | /* [11:10]: RG_VCA15_CSL1; for OC protection */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 162 | pwrap_write_field(PMIC_RG_VCA15_CON1, 0x0, 0x3, 10); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 163 | /* [15:15]: VCA15_SFCHG_REN; soft change rising enable */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 164 | pwrap_write_field(PMIC_RG_VCA15_CON8, 0x1, 0x1, 15); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 165 | /* [14:8]: VCA15_SFCHG_RRATE; soft change rising step=0.5 */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 166 | pwrap_write_field(PMIC_RG_VCA15_CON8, 0x5, 0x7F, 8); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 167 | /* [7:7]: VCA15_SFCHG_FEN; soft change falling enable */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 168 | pwrap_write_field(PMIC_RG_VCA15_CON8, 0x1, 0x1, 7); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 169 | /* [6:0]: VCA15_SFCHG_FRATE; soft change falling step=2us */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 170 | pwrap_write_field(PMIC_RG_VCA15_CON8, 0x17, 0x7F, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 171 | /* [6:0]: VCA15_VOSEL_SLEEP; sleep mode only (0.7V) */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 172 | pwrap_write_field(PMIC_RG_VCA15_CON11, 0x0, 0x7F, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 173 | /* [8:8]: VCA15_VSLEEP_EN; set sleep mode reference volt */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 174 | pwrap_write_field(PMIC_RG_VCA15_CON18, 0x1, 0x1, 8); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 175 | /* [5:4]: VCA15_VOSEL_TRANS_EN; rising & falling enable */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 176 | pwrap_write_field(PMIC_RG_VCA15_CON18, 0x3, 0x3, 4); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 177 | /* [5:5]: VSRMCA15_TRACK_SLEEP_CTRL; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 178 | pwrap_write_field(PMIC_RG_VSRMCA15_CON5, 0x1, 0x1, 5); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 179 | /* [5:4]: VSRMCA15_VOSEL_SEL; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 180 | pwrap_write_field(PMIC_RG_VSRMCA15_CON6, 0x0, 0x3, 4); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 181 | /* [15:15]: VSRMCA15_SFCHG_REN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 182 | pwrap_write_field(PMIC_RG_VSRMCA15_CON8, 0x1, 0x1, 15); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 183 | /* [14:8]: VSRMCA15_SFCHG_RRATE; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 184 | pwrap_write_field(PMIC_RG_VSRMCA15_CON8, 0x5, 0x7F, 8); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 185 | /* [7:7]: VSRMCA15_SFCHG_FEN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 186 | pwrap_write_field(PMIC_RG_VSRMCA15_CON8, 0x1, 0x1, 7); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 187 | /* [6:0]: VSRMCA15_SFCHG_FRATE; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 188 | pwrap_write_field(PMIC_RG_VSRMCA15_CON8, 0x17, 0x7F, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 189 | /* [6:0]: VSRMCA15_VOSEL_SLEEP; Sleep mode setting on */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 190 | pwrap_write_field(PMIC_RG_VSRMCA15_CON11, 0x00, 0x7F, 0); |
Elyes HAOUAS | 1f220a9 | 2020-02-20 14:17:55 +0100 | [diff] [blame] | 191 | /* [8:8]: VSRMCA15_VSLEEP_EN; set sleep mode reference */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 192 | pwrap_write_field(PMIC_RG_VSRMCA15_CON18, 0x1, 0x1, 8); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 193 | /* [5:4]: VSRMCA15_VOSEL_TRANS_EN; rising & falling e */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 194 | pwrap_write_field(PMIC_RG_VSRMCA15_CON18, 0x3, 0x3, 4); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 195 | /* [1:1]: VCORE_VOSEL_CTRL; sleep mode voltage control fo */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 196 | pwrap_write_field(PMIC_RG_VCORE_CON5, 0x1, 0x1, 1); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 197 | /* [5:4]: VCORE_VOSEL_SEL; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 198 | pwrap_write_field(PMIC_RG_VCORE_CON6, 0x0, 0x3, 4); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 199 | /* [15:15]: VCORE_SFCHG_REN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 200 | pwrap_write_field(PMIC_RG_VCORE_CON8, 0x1, 0x1, 15); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 201 | /* [14:8]: VCORE_SFCHG_RRATE; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 202 | pwrap_write_field(PMIC_RG_VCORE_CON8, 0x5, 0x7F, 8); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 203 | /* [6:0]: VCORE_SFCHG_FRATE; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 204 | pwrap_write_field(PMIC_RG_VCORE_CON8, 0x17, 0x7F, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 205 | /* [6:0]: VCORE_VOSEL_SLEEP; Sleep mode setting only (0. */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 206 | pwrap_write_field(PMIC_RG_VCORE_CON11, 0x0, 0x7F, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 207 | /* [8:8]: VCORE_VSLEEP_EN; Sleep mode HW control R2R to */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 208 | pwrap_write_field(PMIC_RG_VCORE_CON18, 0x1, 0x1, 8); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 209 | /* [5:4]: VCORE_VOSEL_TRANS_EN; Follows MT6320 VCORE set */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 210 | pwrap_write_field(PMIC_RG_VCORE_CON18, 0x0, 0x3, 4); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 211 | /* [1:0]: VCORE_TRANSTD; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 212 | pwrap_write_field(PMIC_RG_VCORE_CON18, 0x3, 0x3, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 213 | /* [9:8]: RG_VGPU_CSL; for OC protection */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 214 | pwrap_write_field(PMIC_RG_VGPU_CON1, 0x1, 0x3, 8); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 215 | /* [15:15]: VGPU_SFCHG_REN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 216 | pwrap_write_field(PMIC_RG_VGPU_CON8, 0x1, 0x1, 15); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 217 | /* [14:8]: VGPU_SFCHG_RRATE; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 218 | pwrap_write_field(PMIC_RG_VGPU_CON8, 0x5, 0x7F, 8); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 219 | /* [6:0]: VGPU_SFCHG_FRATE; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 220 | pwrap_write_field(PMIC_RG_VGPU_CON8, 0x17, 0x7F, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 221 | /* [5:4]: VGPU_VOSEL_TRANS_EN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 222 | pwrap_write_field(PMIC_RG_VGPU_CON18, 0x0, 0x3, 4); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 223 | /* [1:0]: VGPU_TRANSTD; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 224 | pwrap_write_field(PMIC_RG_VGPU_CON18, 0x3, 0x3, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 225 | /* [5:4]: VPCA7_VOSEL_SEL; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 226 | pwrap_write_field(PMIC_RG_VPCA7_CON6, 0x0, 0x3, 4); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 227 | /* [15:15]: VPCA7_SFCHG_REN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 228 | pwrap_write_field(PMIC_RG_VPCA7_CON8, 0x1, 0x1, 15); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 229 | /* [14:8]: VPCA7_SFCHG_RRATE; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 230 | pwrap_write_field(PMIC_RG_VPCA7_CON8, 0x5, 0x7F, 8); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 231 | /* [7:7]: VPCA7_SFCHG_FEN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 232 | pwrap_write_field(PMIC_RG_VPCA7_CON8, 0x1, 0x1, 7); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 233 | /* [6:0]: VPCA7_SFCHG_FRATE; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 234 | pwrap_write_field(PMIC_RG_VPCA7_CON8, 0x17, 0x7F, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 235 | /* [6:0]: VPCA7_VOSEL_SLEEP; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 236 | pwrap_write_field(PMIC_RG_VPCA7_CON11, 0x18, 0x7F, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 237 | /* [8:8]: VPCA7_VSLEEP_EN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 238 | pwrap_write_field(PMIC_RG_VPCA7_CON18, 0x0, 0x1, 8); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 239 | /* [5:4]: VPCA7_VOSEL_TRANS_EN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 240 | pwrap_write_field(PMIC_RG_VPCA7_CON18, 0x3, 0x3, 4); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 241 | /* [5:5]: VSRMCA7_TRACK_SLEEP_CTRL; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 242 | pwrap_write_field(PMIC_RG_VSRMCA7_CON5, 0x0, 0x1, 5); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 243 | /* [5:4]: VSRMCA7_VOSEL_SEL; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 244 | pwrap_write_field(PMIC_RG_VSRMCA7_CON6, 0x0, 0x3, 4); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 245 | /* [15:15]: VSRMCA7_SFCHG_REN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 246 | pwrap_write_field(PMIC_RG_VSRMCA7_CON8, 0x1, 0x1, 15); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 247 | /* [14:8]: VSRMCA7_SFCHG_RRATE; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 248 | pwrap_write_field(PMIC_RG_VSRMCA7_CON8, 0x5, 0x7F, 8); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 249 | /* [7:7]: VSRMCA7_SFCHG_FEN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 250 | pwrap_write_field(PMIC_RG_VSRMCA7_CON8, 0x1, 0x1, 7); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 251 | /* [6:0]: VSRMCA7_SFCHG_FRATE; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 252 | pwrap_write_field(PMIC_RG_VSRMCA7_CON8, 0x17, 0x7F, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 253 | /* [6:0]: VSRMCA7_VOSEL_SLEEP; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 254 | pwrap_write_field(PMIC_RG_VSRMCA7_CON11, 0x18, 0x7F, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 255 | /* [8:8]: VSRMCA7_VSLEEP_EN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 256 | pwrap_write_field(PMIC_RG_VSRMCA7_CON18, 0x0, 0x1, 8); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 257 | /* [5:4]: VSRMCA7_VOSEL_TRANS_EN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 258 | pwrap_write_field(PMIC_RG_VSRMCA7_CON18, 0x3, 0x3, 4); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 259 | /* [8:8]: VDRM_VSLEEP_EN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 260 | pwrap_write_field(PMIC_RG_VDRM_CON18, 0x1, 0x1, 8); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 261 | /* [2:2]: VIBR_THER_SHEN_EN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 262 | pwrap_write_field(PMIC_RG_DIGLDO_CON24, 0x1, 0x1, 2); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 263 | /* [5:5]: THR_HWPDN_EN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 264 | pwrap_write_field(PMIC_RG_STRUP_CON0, 0x1, 0x1, 5); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 265 | /* [3:3]: RG_RST_DRVSEL; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 266 | pwrap_write_field(PMIC_RG_STRUP_CON2, 0x1, 0x1, 3); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 267 | /* [2:2]: RG_EN_DRVSEL; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 268 | pwrap_write_field(PMIC_RG_STRUP_CON2, 0x1, 0x1, 2); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 269 | /* [1:1]: PWRBB_DEB_EN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 270 | pwrap_write_field(PMIC_RG_STRUP_CON5, 0x1, 0x1, 1); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 271 | /* [12:12]: VSRMCA15_PG_H2L_EN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 272 | pwrap_write_field(PMIC_RG_STRUP_CON7, 0x1, 0x1, 12); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 273 | /* [11:11]: VPCA15_PG_H2L_EN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 274 | pwrap_write_field(PMIC_RG_STRUP_CON7, 0x1, 0x1, 11); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 275 | /* [10:10]: VCORE_PG_H2L_EN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 276 | pwrap_write_field(PMIC_RG_STRUP_CON7, 0x1, 0x1, 10); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 277 | /* [9:9]: VSRMCA7_PG_H2L_EN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 278 | pwrap_write_field(PMIC_RG_STRUP_CON7, 0x1, 0x1, 9); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 279 | /* [8:8]: VPCA7_PG_H2L_EN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 280 | pwrap_write_field(PMIC_RG_STRUP_CON7, 0x1, 0x1, 8); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 281 | /* [1:1]: STRUP_PWROFF_PREOFF_EN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 282 | pwrap_write_field(PMIC_RG_STRUP_CON10, 0x1, 0x1, 1); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 283 | /* [0:0]: STRUP_PWROFF_SEQ_EN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 284 | pwrap_write_field(PMIC_RG_STRUP_CON10, 0x1, 0x1, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 285 | /* [15:8]: RG_ADC_TRIM_CH_SEL; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 286 | pwrap_write_field(PMIC_RG_AUXADC_CON14, 0xFC, 0xFF, 8); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 287 | /* [1:1]: FLASH_THER_SHDN_EN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 288 | pwrap_write_field(PMIC_RG_FLASH_CON0, 0x1, 0x1, 1); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 289 | /* [1:1]: KPLED_THER_SHDN_EN; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 290 | pwrap_write_field(PMIC_RG_KPLED_CON0, 0x1, 0x1, 1); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 291 | /* [14:8]: VSRMCA15_VOSEL_OFFSET; set offset=100mV */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 292 | pwrap_write_field(PMIC_RG_VSRMCA15_CON19, 0x10, 0x7F, 8); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 293 | /* [6:0]: VSRMCA15_VOSEL_DELTA; set delta=0mV */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 294 | pwrap_write_field(PMIC_RG_VSRMCA15_CON19, 0x0, 0x7F, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 295 | /* [14:8]: VSRMCA15_VOSEL_ON_HB; set HB=1.15V */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 296 | pwrap_write_field(PMIC_RG_VSRMCA15_CON20, 0x48, 0x7F, 8); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 297 | /* [6:0]: VSRMCA15_VOSEL_ON_LB; set LB=0.7V */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 298 | pwrap_write_field(PMIC_RG_VSRMCA15_CON20, 0x0, 0x7F, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 299 | /* [6:0]: VSRMCA15_VOSEL_SLEEP_LB; set sleep LB=0.7V */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 300 | pwrap_write_field(PMIC_RG_VSRMCA15_CON21, 0x0, 0x7F, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 301 | /* [14:8]: VSRMCA7_VOSEL_OFFSET; set offset=25mV */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 302 | pwrap_write_field(PMIC_RG_VSRMCA7_CON19, 0x4, 0x7F, 8); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 303 | /* [6:0]: VSRMCA7_VOSEL_DELTA; set delta=0mV */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 304 | pwrap_write_field(PMIC_RG_VSRMCA7_CON19, 0x0, 0x7F, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 305 | /* [14:8]: VSRMCA7_VOSEL_ON_HB; set HB=1.275V */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 306 | pwrap_write_field(PMIC_RG_VSRMCA7_CON20, 0x5C, 0x7F, 8); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 307 | /* [6:0]: VSRMCA7_VOSEL_ON_LB; set LB=1.05000V */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 308 | pwrap_write_field(PMIC_RG_VSRMCA7_CON20, 0x38, 0x7F, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 309 | /* [6:0]: VSRMCA7_VOSEL_SLEEP_LB; set sleep LB=0.85000 */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 310 | pwrap_write_field(PMIC_RG_VSRMCA7_CON21, 0x18, 0x7F, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 311 | /* [1:1]: VCA15_VOSEL_CTRL, VCA15_EN_CTRL; DVS HW control */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 312 | pwrap_write_field(PMIC_RG_VCA15_CON5, 0x3, 0x3, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 313 | /* [1:1]: VSRMCA15_VOSEL_CTRL, VSRAM15_EN_CTRL; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 314 | pwrap_write_field(PMIC_RG_VSRMCA15_CON5, 0x3, 0x3, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 315 | /* [1:1]: VPCA7_VOSEL_CTRL; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 316 | pwrap_write_field(PMIC_RG_VPCA7_CON5, 0x0, 0x1, 1); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 317 | /* [1:1]: VSRMCA7_VOSEL_CTRL; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 318 | pwrap_write_field(PMIC_RG_VSRMCA7_CON5, 0x0, 0x1, 1); |
henryc.chen | aad2903 | 2016-03-07 15:17:01 +0800 | [diff] [blame] | 319 | /* [0:0]: VSRMCA7_EN_CTRL; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 320 | pwrap_write_field(PMIC_RG_VSRMCA7_CON5, 0x1, 0x1, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 321 | /* [4:4]: VCA15_TRACK_ON_CTRL; DVFS tracking enable */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 322 | pwrap_write_field(PMIC_RG_VCA15_CON5, 0x1, 0x1, 4); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 323 | /* [4:4]: VSRMCA15_TRACK_ON_CTRL; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 324 | pwrap_write_field(PMIC_RG_VSRMCA15_CON5, 0x1, 0x1, 4); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 325 | /* [4:4]: VPCA7_TRACK_ON_CTRL; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 326 | pwrap_write_field(PMIC_RG_VPCA7_CON5, 0x0, 0x1, 4); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 327 | /* [4:4]: VSRMCA7_TRACK_ON_CTRL; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 328 | pwrap_write_field(PMIC_RG_VSRMCA7_CON5, 0x0, 0x1, 4); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 329 | /* [15:14]: VGPU OC; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 330 | pwrap_write_field(PMIC_RG_OC_CTL1, 0x3, 0x3, 14); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 331 | /* [3:2]: VCA15 OC; */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 332 | pwrap_write_field(PMIC_RG_OC_CTL1, 0x3, 0x3, 2); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 333 | |
| 334 | /* Set VPCA7 to 1.2V */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 335 | pwrap_write_field(PMIC_RG_VPCA7_CON9, 0x50, 0x7f, 0x0); |
| 336 | pwrap_write_field(PMIC_RG_VPCA7_CON10, 0x50, 0x7f, 0x0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 337 | /* Set VSRMCA7 to 1.1V */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 338 | pwrap_write_field(PMIC_RG_VSRMCA7_CON9, 0x40, 0x7f, 0x0); |
| 339 | pwrap_write_field(PMIC_RG_VSRMCA7_CON10, 0x40, 0x7f, 0x0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 340 | |
| 341 | /* Enable VGP6 and set to 3.3V*/ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 342 | pwrap_write_field(PMIC_RG_DIGLDO_CON10, 0x1, 0x1, 15); |
| 343 | pwrap_write_field(PMIC_RG_DIGLDO_CON33, 0x07, 0x07, 5); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 344 | |
| 345 | /* Set VDRM to 1.21875V */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 346 | pwrap_write_field(PMIC_RG_VDRM_CON9, 0x43, 0x7F, 0); |
| 347 | pwrap_write_field(PMIC_RG_VDRM_CON10, 0x43, 0x7F, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 348 | |
Elyes HAOUAS | 1f220a9 | 2020-02-20 14:17:55 +0100 | [diff] [blame] | 349 | /* 26M clock amplitude adjust */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 350 | pwrap_write_field(PMIC_RG_DCXO_ANALOG_CON1, 0x0, 0x3, 2); |
| 351 | pwrap_write_field(PMIC_RG_DCXO_ANALOG_CON1, 0x1, 0x3, 11); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 352 | |
| 353 | /* For low power, set VTCXO switch by SRCVOLTEN */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 354 | pwrap_write_field(PMIC_RG_DIGLDO_CON27, 0x0100, 0x0100, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 355 | /* [6:5]=0(VTCXO_SRCLK_MODE_SEL) */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 356 | pwrap_write_field(PMIC_RG_ANALDO_CON0, 0, 0x3, 13); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 357 | /* [11]=0(VTCXO_ON_CTRL), */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 358 | pwrap_write_field(PMIC_RG_ANALDO_CON0, 1, 0x1, 11); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 359 | /* [10]=1(RG_VTCXO_EN), */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 360 | pwrap_write_field(PMIC_RG_ANALDO_CON0, 1, 0x1, 10); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 361 | /* [4:3]=1(RG_VTCXOTD_SEL) */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 362 | pwrap_write_field(PMIC_RG_ANALDO_CON0, 0x3, 0x3, 3); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 363 | /* For low power, VIO18 set sleep_en to HW mode */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 364 | pwrap_write_field(PMIC_RG_VIO18_CON18, 0x1, 0x1, 8); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 365 | |
| 366 | } |
| 367 | |
| 368 | static void mt6391_default_buck_voltage(void) |
| 369 | { |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 370 | u16 reg = 0; |
| 371 | u16 buck = 0; |
Paul Menzel | 454cfa0 | 2017-10-24 15:38:51 +0200 | [diff] [blame] | 372 | /* |
| 373 | * There are two kinds of PMIC used for MT8173 : MT6397s/MT6391. |
| 374 | * |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 375 | * MT6397s: the default voltage of register was not suitable for |
| 376 | * MT8173, needs to apply the setting of eFuse. |
| 377 | * VPCA15/VSRMCA15/: 1.15V |
| 378 | * VCORE: 1.05V |
| 379 | * |
| 380 | * MT6391: the default voltage of register was matched for MT8173. |
| 381 | * VPAC15/VCORE/VGPU: 1.0V |
| 382 | * VSRMCA15: 1.0125V |
| 383 | */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 384 | reg = pwrap_read_field(PMIC_RG_EFUSE_DOUT_288_303, 0xFFFF, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 385 | |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 386 | if ((reg & 0x01) == 0x01) { |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 387 | /* VCORE */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 388 | reg = pwrap_read_field(PMIC_RG_EFUSE_DOUT_256_271, 0xF, 12); |
| 389 | buck = pwrap_read_field(PMIC_RG_VCORE_CON9, 0x7f, 0x0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 390 | |
| 391 | /* VCORE_VOSEL[3:6] => eFuse bit 268-271 */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 392 | buck = (buck & 0x07) | (reg << 3); |
| 393 | pwrap_write_field(PMIC_RG_VCORE_CON9, buck, 0x7f, 0x0); |
| 394 | pwrap_write_field(PMIC_RG_VCORE_CON10, buck, 0x7f, 0x0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 395 | |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 396 | reg = pwrap_read_field(PMIC_RG_EFUSE_DOUT_272_287, 0xFFFF, 0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 397 | /* VCA15 */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 398 | buck = 0; |
| 399 | buck = pwrap_read_field(PMIC_RG_VCA15_CON9, 0x7f, 0x0); |
| 400 | buck = (buck & 0x07) | ((reg & 0x0F) << 3); |
| 401 | pwrap_write_field(PMIC_RG_VCA15_CON9, buck, 0x7f, 0x0); |
| 402 | pwrap_write_field(PMIC_RG_VCA15_CON10, buck, 0x7f, 0x0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 403 | |
| 404 | /* VSAMRCA15 */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 405 | buck = 0; |
| 406 | buck = pwrap_read_field(PMIC_RG_VSRMCA15_CON9, 0x7f, 0x0); |
| 407 | buck = (buck & 0x07) | ((reg & 0xF0) >> 1); |
| 408 | pwrap_write_field(PMIC_RG_VSRMCA15_CON9, buck, 0x7f, 0x0); |
| 409 | pwrap_write_field(PMIC_RG_VSRMCA15_CON10, buck, 0x7f, 0x0); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 410 | |
| 411 | /* set the power control by register(use original) */ |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 412 | pwrap_write_field(PMIC_RG_BUCK_CON3, 0x1, 0x1, 12); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 413 | } |
| 414 | } |
| 415 | |
| 416 | void mt6391_init(void) |
| 417 | { |
| 418 | if (pwrap_init()) |
Paul Menzel | 22db82d | 2017-10-24 15:40:18 +0200 | [diff] [blame] | 419 | die("ERROR - Failed to initialize pmic wrap!"); |
henryc.chen | 31ae314 | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 420 | /* pmic initial setting */ |
| 421 | mt6391_init_setting(); |
| 422 | |
| 423 | /* Adjust default BUCK voltage from eFuse */ |
| 424 | mt6391_default_buck_voltage(); |
| 425 | } |
Biao Huang | 0dd8315 | 2015-09-03 17:39:12 +0800 | [diff] [blame] | 426 | |
| 427 | /* API of GPIO in PMIC MT6391 */ |
| 428 | enum { |
| 429 | MAX_GPIO_REG_BITS = 16, |
| 430 | MAX_GPIO_MODE_PER_REG = 5, |
| 431 | GPIO_MODE_BITS = 3, |
| 432 | GPIO_PORT_OFFSET = 3, |
| 433 | GPIO_SET_OFFSET = 2, |
| 434 | GPIO_RST_OFFSET = 4, |
| 435 | MAX_MT6391_GPIO = 40 |
| 436 | }; |
| 437 | |
| 438 | enum { |
| 439 | MT6391_GPIO_DIRECTION_IN = 0, |
| 440 | MT6391_GPIO_DIRECTION_OUT = 1, |
| 441 | }; |
| 442 | |
| 443 | enum { |
| 444 | MT6391_GPIO_MODE = 0, |
| 445 | }; |
| 446 | |
| 447 | static void pos_bit_calc(u32 pin, u16 *pos, u16 *bit) |
| 448 | { |
| 449 | *pos = (pin / MAX_GPIO_REG_BITS) << GPIO_PORT_OFFSET; |
| 450 | *bit = pin % MAX_GPIO_REG_BITS; |
| 451 | } |
| 452 | |
| 453 | static void pos_bit_calc_mode(u32 pin, u16 *pos, u16 *bit) |
| 454 | { |
| 455 | *pos = (pin / MAX_GPIO_MODE_PER_REG) << GPIO_PORT_OFFSET; |
| 456 | *bit = (pin % MAX_GPIO_MODE_PER_REG) * GPIO_MODE_BITS; |
| 457 | } |
| 458 | |
| 459 | static s32 mt6391_gpio_set_dir(u32 pin, u32 dir) |
| 460 | { |
| 461 | u16 pos; |
| 462 | u16 bit; |
| 463 | u16 reg; |
| 464 | |
| 465 | assert(pin <= MAX_MT6391_GPIO); |
| 466 | |
| 467 | pos_bit_calc(pin, &pos, &bit); |
| 468 | |
| 469 | if (dir == MT6391_GPIO_DIRECTION_IN) |
| 470 | reg = MT6391_GPIO_DIR_BASE + pos + GPIO_RST_OFFSET; |
| 471 | else |
| 472 | reg = MT6391_GPIO_DIR_BASE + pos + GPIO_SET_OFFSET; |
| 473 | |
| 474 | if (pwrap_write(reg, 1L << bit) != 0) |
| 475 | return -1; |
| 476 | |
| 477 | return 0; |
| 478 | } |
| 479 | |
| 480 | void mt6391_gpio_set_pull(u32 pin, enum mt6391_pull_enable enable, |
| 481 | enum mt6391_pull_select select) |
| 482 | { |
| 483 | u16 pos; |
| 484 | u16 bit; |
| 485 | u16 en_reg, sel_reg; |
| 486 | |
| 487 | assert(pin <= MAX_MT6391_GPIO); |
| 488 | |
| 489 | pos_bit_calc(pin, &pos, &bit); |
| 490 | |
| 491 | if (enable == MT6391_GPIO_PULL_DISABLE) { |
| 492 | en_reg = MT6391_GPIO_PULLEN_BASE + pos + GPIO_RST_OFFSET; |
| 493 | } else { |
| 494 | en_reg = MT6391_GPIO_PULLEN_BASE + pos + GPIO_SET_OFFSET; |
| 495 | sel_reg = (select == MT6391_GPIO_PULL_DOWN) ? |
| 496 | (MT6391_GPIO_PULLSEL_BASE + pos + GPIO_RST_OFFSET) : |
| 497 | (MT6391_GPIO_PULLSEL_BASE + pos + GPIO_SET_OFFSET); |
| 498 | pwrap_write(sel_reg, 1L << bit); |
| 499 | } |
| 500 | pwrap_write(en_reg, 1L << bit); |
| 501 | } |
| 502 | |
| 503 | int mt6391_gpio_get(u32 pin) |
| 504 | { |
| 505 | u16 pos; |
| 506 | u16 bit; |
| 507 | u16 reg; |
| 508 | u16 data; |
| 509 | |
| 510 | assert(pin <= MAX_MT6391_GPIO); |
| 511 | |
| 512 | pos_bit_calc(pin, &pos, &bit); |
| 513 | |
| 514 | reg = MT6391_GPIO_DIN_BASE + pos; |
| 515 | pwrap_read(reg, &data); |
| 516 | |
| 517 | return (data & (1L << bit)) ? 1 : 0; |
| 518 | } |
| 519 | |
| 520 | void mt6391_gpio_set(u32 pin, int output) |
| 521 | { |
| 522 | u16 pos; |
| 523 | u16 bit; |
| 524 | u16 reg; |
| 525 | |
| 526 | assert(pin <= MAX_MT6391_GPIO); |
| 527 | |
| 528 | pos_bit_calc(pin, &pos, &bit); |
| 529 | |
| 530 | if (output == 0) |
| 531 | reg = MT6391_GPIO_DOUT_BASE + pos + GPIO_RST_OFFSET; |
| 532 | else |
| 533 | reg = MT6391_GPIO_DOUT_BASE + pos + GPIO_SET_OFFSET; |
| 534 | |
| 535 | pwrap_write(reg, 1L << bit); |
| 536 | } |
| 537 | |
| 538 | void mt6391_gpio_set_mode(u32 pin, int mode) |
| 539 | { |
| 540 | u16 pos; |
| 541 | u16 bit; |
| 542 | u16 mask = (1L << GPIO_MODE_BITS) - 1; |
| 543 | |
| 544 | assert(pin <= MAX_MT6391_GPIO); |
| 545 | |
| 546 | pos_bit_calc_mode(pin, &pos, &bit); |
Tristan Shieh | ab1b83d | 2018-11-01 18:01:50 +0800 | [diff] [blame] | 547 | pwrap_write_field(MT6391_GPIO_MODE_BASE + pos, mode, mask, bit); |
Biao Huang | 0dd8315 | 2015-09-03 17:39:12 +0800 | [diff] [blame] | 548 | } |
| 549 | |
| 550 | void mt6391_gpio_input_pulldown(u32 gpio) |
| 551 | { |
| 552 | mt6391_gpio_set_pull(gpio, MT6391_GPIO_PULL_ENABLE, |
| 553 | MT6391_GPIO_PULL_DOWN); |
| 554 | mt6391_gpio_set_dir(gpio, MT6391_GPIO_DIRECTION_IN); |
| 555 | mt6391_gpio_set_mode(gpio, MT6391_GPIO_MODE); |
| 556 | } |
| 557 | |
| 558 | void mt6391_gpio_input_pullup(u32 gpio) |
| 559 | { |
| 560 | mt6391_gpio_set_pull(gpio, MT6391_GPIO_PULL_ENABLE, |
| 561 | MT6391_GPIO_PULL_UP); |
| 562 | mt6391_gpio_set_dir(gpio, MT6391_GPIO_DIRECTION_IN); |
| 563 | mt6391_gpio_set_mode(gpio, MT6391_GPIO_MODE); |
| 564 | } |
| 565 | |
| 566 | void mt6391_gpio_input(u32 gpio) |
| 567 | { |
| 568 | mt6391_gpio_set_pull(gpio, MT6391_GPIO_PULL_DISABLE, |
| 569 | MT6391_GPIO_PULL_DOWN); |
| 570 | mt6391_gpio_set_dir(gpio, MT6391_GPIO_DIRECTION_IN); |
| 571 | mt6391_gpio_set_mode(gpio, MT6391_GPIO_MODE); |
| 572 | } |
| 573 | |
| 574 | void mt6391_gpio_output(u32 gpio, int value) |
| 575 | { |
| 576 | mt6391_gpio_set_pull(gpio, MT6391_GPIO_PULL_DISABLE, |
| 577 | MT6391_GPIO_PULL_DOWN); |
| 578 | mt6391_gpio_set(gpio, value); |
| 579 | mt6391_gpio_set_dir(gpio, MT6391_GPIO_DIRECTION_OUT); |
| 580 | mt6391_gpio_set_mode(gpio, MT6391_GPIO_MODE); |
| 581 | } |