Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2013 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 15 | */ |
| 16 | |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 17 | #include <device/mmio.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 18 | #include <device/pci_ops.h> |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 19 | #include <cbmem.h> |
| 20 | #include <console/console.h> |
| 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 23 | #include <device/pci_ids.h> |
| 24 | #include <stdlib.h> |
| 25 | #include "pch.h" |
| 26 | #include "nvs.h" |
| 27 | |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 28 | /* Enable clock in PCI mode */ |
| 29 | static void serialio_enable_clock(struct resource *bar0) |
| 30 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 31 | u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0)); |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 32 | reg32 |= SIO_REG_PPR_CLOCK_EN; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 33 | write32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0), reg32); |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 34 | } |
| 35 | |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 36 | /* Put Serial IO D21:F0-F6 device into desired mode. */ |
| 37 | static void serialio_d21_mode(int sio_index, int int_pin, int acpi_mode) |
| 38 | { |
| 39 | u32 portctrl = SIO_IOBP_PORTCTRL_PM_CAP_PRSNT; |
| 40 | |
| 41 | /* Snoop select 1. */ |
| 42 | portctrl |= SIO_IOBP_PORTCTRL_SNOOP_SELECT(1); |
| 43 | |
| 44 | /* Set interrupt pin. */ |
| 45 | portctrl |= SIO_IOBP_PORTCTRL_INT_PIN(int_pin); |
| 46 | |
| 47 | if (acpi_mode) { |
| 48 | /* Enable ACPI interrupt mode. */ |
| 49 | portctrl |= SIO_IOBP_PORTCTRL_ACPI_IRQ_EN; |
| 50 | |
| 51 | /* Disable PCI config space. */ |
| 52 | portctrl |= SIO_IOBP_PORTCTRL_PCI_CONF_DIS; |
| 53 | } |
| 54 | |
| 55 | pch_iobp_update(SIO_IOBP_PORTCTRLX(sio_index), 0, portctrl); |
| 56 | } |
| 57 | |
| 58 | /* Put Serial IO D23:F0 device into desired mode. */ |
| 59 | static void serialio_d23_mode(int acpi_mode) |
| 60 | { |
| 61 | u32 portctrl = 0; |
| 62 | |
| 63 | /* Snoop select 1. */ |
| 64 | pch_iobp_update(SIO_IOBP_PORTCTRL1, 0, |
| 65 | SIO_IOBP_PORTCTRL1_SNOOP_SELECT(1)); |
| 66 | |
| 67 | if (acpi_mode) { |
| 68 | /* Enable ACPI interrupt mode. */ |
| 69 | portctrl |= SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN; |
| 70 | |
| 71 | /* Disable PCI config space. */ |
| 72 | portctrl |= SIO_IOBP_PORTCTRL0_PCI_CONF_DIS; |
| 73 | } |
| 74 | |
| 75 | pch_iobp_update(SIO_IOBP_PORTCTRL0, 0, portctrl); |
| 76 | } |
| 77 | |
| 78 | /* Enable LTR Auto Mode for D21:F1-F6. */ |
| 79 | static void serialio_d21_ltr(struct resource *bar0) |
| 80 | { |
| 81 | u32 reg; |
| 82 | |
| 83 | /* 1. Program BAR0 + 808h[2] = 0b */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 84 | reg = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0)); |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 85 | reg &= ~SIO_REG_PPR_GEN_LTR_MODE_MASK; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 86 | write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg); |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 87 | |
| 88 | /* 2. Program BAR0 + 804h[1:0] = 00b */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 89 | reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0)); |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 90 | reg &= ~SIO_REG_PPR_RST_ASSERT; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 91 | write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg); |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 92 | |
| 93 | /* 3. Program BAR0 + 804h[1:0] = 11b */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 94 | reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0)); |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 95 | reg |= SIO_REG_PPR_RST_ASSERT; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 96 | write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg); |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 97 | |
| 98 | /* 4. Program BAR0 + 814h[31:0] = 00000000h */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 99 | write32(res2mmio(bar0, SIO_REG_AUTO_LTR, 0), 0); |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 100 | } |
| 101 | |
| 102 | /* Enable LTR Auto Mode for D23:F0. */ |
| 103 | static void serialio_d23_ltr(struct resource *bar0) |
| 104 | { |
| 105 | u32 reg; |
| 106 | |
| 107 | /* Program BAR0 + 1008h[2] = 1b */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 108 | reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0)); |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 109 | reg |= SIO_REG_PPR_GEN_LTR_MODE_MASK; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 110 | write32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0), reg); |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 111 | |
| 112 | /* Program BAR0 + 1010h = 0x00000000 */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 113 | write32(res2mmio(bar0, SIO_REG_SDIO_PPR_SW_LTR, 0), 0); |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 114 | |
| 115 | /* Program BAR0 + 3Ch[30] = 1b */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 116 | reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0)); |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 117 | reg |= SIO_REG_SDIO_PPR_CMD12_B30; |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 118 | write32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0), reg); |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 119 | } |
| 120 | |
| 121 | /* Select I2C voltage of 1.8V or 3.3V. */ |
| 122 | static void serialio_i2c_voltage_sel(struct resource *bar0, u8 voltage) |
| 123 | { |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 124 | u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0)); |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 125 | reg32 &= ~SIO_REG_PPR_GEN_VOLTAGE_MASK; |
| 126 | reg32 |= SIO_REG_PPR_GEN_VOLTAGE(voltage); |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 127 | write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg32); |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 128 | } |
| 129 | |
| 130 | /* Init sequence to be run once, done as part of D21:F0 (SDMA) init. */ |
| 131 | static void serialio_init_once(int acpi_mode) |
| 132 | { |
| 133 | if (acpi_mode) { |
| 134 | /* Enable ACPI IRQ for IRQ13, IRQ7, IRQ6, IRQ5 in RCBA. */ |
| 135 | RCBA32_OR(ACPIIRQEN, (1 << 13)|(1 << 7)|(1 << 6)|(1 << 5)); |
| 136 | } |
| 137 | |
| 138 | /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b. */ |
| 139 | pch_iobp_update(SIO_IOBP_GPIODF, ~0x0000131f, 0x0000131f); |
| 140 | |
| 141 | /* Program IOBP CB000180h[5:0] = 111111b (undefined register) */ |
| 142 | pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f); |
| 143 | } |
| 144 | |
| 145 | static void serialio_init(struct device *dev) |
| 146 | { |
| 147 | struct southbridge_intel_lynxpoint_config *config = dev->chip_info; |
| 148 | struct resource *bar0, *bar1; |
| 149 | int sio_index = -1; |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 150 | u32 reg32; |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 151 | |
| 152 | printk(BIOS_DEBUG, "Initializing Serial IO device\n"); |
| 153 | |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 154 | /* Ensure memory and bus master are enabled */ |
| 155 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 156 | reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
| 157 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 158 | |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 159 | /* Find BAR0 and BAR1 */ |
| 160 | bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 161 | if (!bar0) |
| 162 | return; |
| 163 | bar1 = find_resource(dev, PCI_BASE_ADDRESS_1); |
| 164 | if (!bar1) |
| 165 | return; |
| 166 | |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 167 | if (!config->sio_acpi_mode) |
| 168 | serialio_enable_clock(bar0); |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 169 | |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 170 | switch (dev->path.pci.devfn) { |
| 171 | case PCI_DEVFN(21, 0): /* SDMA */ |
| 172 | sio_index = SIO_ID_SDMA; |
| 173 | serialio_init_once(config->sio_acpi_mode); |
| 174 | serialio_d21_mode(sio_index, SIO_PIN_INTB, |
| 175 | config->sio_acpi_mode); |
| 176 | break; |
| 177 | case PCI_DEVFN(21, 1): /* I2C0 */ |
| 178 | sio_index = SIO_ID_I2C0; |
| 179 | serialio_d21_ltr(bar0); |
| 180 | serialio_i2c_voltage_sel(bar0, config->sio_i2c0_voltage); |
| 181 | serialio_d21_mode(sio_index, SIO_PIN_INTC, |
| 182 | config->sio_acpi_mode); |
| 183 | break; |
| 184 | case PCI_DEVFN(21, 2): /* I2C1 */ |
| 185 | sio_index = SIO_ID_I2C1; |
| 186 | serialio_d21_ltr(bar0); |
| 187 | serialio_i2c_voltage_sel(bar0, config->sio_i2c1_voltage); |
| 188 | serialio_d21_mode(sio_index, SIO_PIN_INTC, |
| 189 | config->sio_acpi_mode); |
| 190 | break; |
| 191 | case PCI_DEVFN(21, 3): /* SPI0 */ |
| 192 | sio_index = SIO_ID_SPI0; |
| 193 | serialio_d21_ltr(bar0); |
| 194 | serialio_d21_mode(sio_index, SIO_PIN_INTC, |
| 195 | config->sio_acpi_mode); |
| 196 | break; |
| 197 | case PCI_DEVFN(21, 4): /* SPI1 */ |
| 198 | sio_index = SIO_ID_SPI1; |
| 199 | serialio_d21_ltr(bar0); |
| 200 | serialio_d21_mode(sio_index, SIO_PIN_INTC, |
| 201 | config->sio_acpi_mode); |
| 202 | break; |
| 203 | case PCI_DEVFN(21, 5): /* UART0 */ |
| 204 | sio_index = SIO_ID_UART0; |
| 205 | serialio_d21_ltr(bar0); |
| 206 | serialio_d21_mode(sio_index, SIO_PIN_INTD, |
| 207 | config->sio_acpi_mode); |
| 208 | break; |
| 209 | case PCI_DEVFN(21, 6): /* UART1 */ |
| 210 | sio_index = SIO_ID_UART1; |
| 211 | serialio_d21_ltr(bar0); |
| 212 | serialio_d21_mode(sio_index, SIO_PIN_INTD, |
| 213 | config->sio_acpi_mode); |
| 214 | break; |
| 215 | case PCI_DEVFN(23, 0): /* SDIO */ |
| 216 | sio_index = SIO_ID_SDIO; |
| 217 | serialio_d23_ltr(bar0); |
| 218 | serialio_d23_mode(config->sio_acpi_mode); |
| 219 | break; |
| 220 | default: |
| 221 | return; |
| 222 | } |
| 223 | |
| 224 | if (config->sio_acpi_mode) { |
| 225 | global_nvs_t *gnvs; |
| 226 | |
| 227 | /* Find ACPI NVS to update BARs */ |
| 228 | gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 229 | if (!gnvs) { |
| 230 | printk(BIOS_ERR, "Unable to locate Global NVS\n"); |
| 231 | return; |
| 232 | } |
| 233 | |
| 234 | /* Save BAR0 and BAR1 to ACPI NVS */ |
| 235 | gnvs->s0b[sio_index] = (u32)bar0->base; |
| 236 | gnvs->s1b[sio_index] = (u32)bar1->base; |
| 237 | } |
| 238 | } |
| 239 | |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 240 | static struct pci_operations pci_ops = { |
Subrata Banik | 4a0f071 | 2019-03-20 14:29:47 +0530 | [diff] [blame^] | 241 | .set_subsystem = pci_dev_set_subsystem, |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 242 | }; |
| 243 | |
| 244 | static struct device_operations device_ops = { |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 245 | .read_resources = pci_dev_read_resources, |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 246 | .set_resources = pci_dev_set_resources, |
Duncan Laurie | 98c4062 | 2013-05-21 16:37:40 -0700 | [diff] [blame] | 247 | .enable_resources = pci_dev_enable_resources, |
Duncan Laurie | b39ba2e | 2013-03-22 11:21:14 -0700 | [diff] [blame] | 248 | .init = serialio_init, |
| 249 | .ops_pci = &pci_ops, |
| 250 | }; |
| 251 | |
| 252 | static const unsigned short pci_device_ids[] = { |
| 253 | 0x9c60, /* 0:15.0 - SDMA */ |
| 254 | 0x9c61, /* 0:15.1 - I2C0 */ |
| 255 | 0x9c62, /* 0:15.2 - I2C1 */ |
| 256 | 0x9c65, /* 0:15.3 - SPI0 */ |
| 257 | 0x9c66, /* 0:15.4 - SPI1 */ |
| 258 | 0x9c63, /* 0:15.5 - UART0 */ |
| 259 | 0x9c64, /* 0:15.6 - UART1 */ |
| 260 | 0x9c35, /* 0:17.0 - SDIO */ |
| 261 | 0 |
| 262 | }; |
| 263 | |
| 264 | static const struct pci_driver pch_pcie __pci_driver = { |
| 265 | .ops = &device_ops, |
| 266 | .vendor = PCI_VENDOR_ID_INTEL, |
| 267 | .devices = pci_device_ids, |
| 268 | }; |