huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Rockchip Electronics |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Patrick Georgi | b890a12 | 2015-03-26 15:17:45 +0100 | [diff] [blame] | 17 | * Foundation, Inc. |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | #include <libpayload.h> |
| 21 | #include <arch/cache.h> |
| 22 | |
| 23 | #include "dwc2.h" |
| 24 | #include "dwc2_private.h" |
| 25 | |
| 26 | static void dummy(hci_t *controller) |
| 27 | { |
| 28 | } |
| 29 | |
| 30 | static void dwc2_reinit(hci_t *controller) |
| 31 | { |
| 32 | dwc2_reg_t *reg = DWC2_REG(controller); |
| 33 | gusbcfg_t gusbcfg = { .d32 = 0 }; |
| 34 | grstctl_t grstctl = { .d32 = 0 }; |
| 35 | gintsts_t gintsts = { .d32 = 0 }; |
| 36 | gahbcfg_t gahbcfg = { .d32 = 0 }; |
| 37 | grxfsiz_t grxfsiz = { .d32 = 0 }; |
huang lin | 8b52c93 | 2014-12-04 18:25:47 +0800 | [diff] [blame] | 38 | ghwcfg3_t hwcfg3 = { .d32 = 0 }; |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 39 | hcintmsk_t hcintmsk = { .d32 = 0 }; |
Yunzhi Li | aa33609 | 2015-06-19 17:09:04 +0800 | [diff] [blame] | 40 | gtxfsiz_t gnptxfsiz = { .d32 = 0 }; |
| 41 | gtxfsiz_t hptxfsiz = { .d32 = 0 }; |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 42 | |
| 43 | const int timeout = 10000; |
huang lin | 8b52c93 | 2014-12-04 18:25:47 +0800 | [diff] [blame] | 44 | int i, fifo_blocks, tx_blocks; |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 45 | |
| 46 | /* Wait for AHB idle */ |
| 47 | for (i = 0; i < timeout; i++) { |
| 48 | udelay(1); |
| 49 | grstctl.d32 = readl(®->core.grstctl); |
| 50 | if (grstctl.ahbidle) |
| 51 | break; |
| 52 | } |
| 53 | if (i == timeout) |
| 54 | fatal("DWC2 Init error AHB Idle\n"); |
| 55 | |
| 56 | /* Restart the Phy Clock */ |
| 57 | writel(0x0, ®->pcgr.pcgcctl); |
| 58 | /* Core soft reset */ |
| 59 | grstctl.csftrst = 1; |
| 60 | writel(grstctl.d32, ®->core.grstctl); |
| 61 | for (i = 0; i < timeout; i++) { |
| 62 | udelay(1); |
| 63 | grstctl.d32 = readl(®->core.grstctl); |
| 64 | if (!grstctl.csftrst) |
| 65 | break; |
| 66 | } |
| 67 | if (i == timeout) |
| 68 | fatal("DWC2 Init error reset fail\n"); |
| 69 | |
| 70 | /* Set 16bit PHY if & Force host mode */ |
| 71 | gusbcfg.d32 = readl(®->core.gusbcfg); |
| 72 | gusbcfg.phyif = 1; |
| 73 | gusbcfg.forcehstmode = 1; |
| 74 | gusbcfg.forcedevmode = 0; |
| 75 | writel(gusbcfg.d32, ®->core.gusbcfg); |
| 76 | /* Wait for force host mode effect, it may takes 100ms */ |
| 77 | for (i = 0; i < timeout; i++) { |
| 78 | udelay(10); |
| 79 | gintsts.d32 = readl(®->core.gintsts); |
| 80 | if (gintsts.curmod) |
| 81 | break; |
| 82 | } |
| 83 | if (i == timeout) |
| 84 | fatal("DWC2 Init error force host mode fail\n"); |
| 85 | |
| 86 | /* |
| 87 | * Config FIFO |
| 88 | * The non-periodic tx fifo and rx fifo share one continuous |
| 89 | * piece of IP-internal SRAM. |
| 90 | */ |
huang lin | 8b52c93 | 2014-12-04 18:25:47 +0800 | [diff] [blame] | 91 | |
| 92 | /* |
| 93 | * Read total data FIFO depth from HWCFG3 |
| 94 | * this value is in terms of 32-bit words |
| 95 | */ |
| 96 | hwcfg3.d32 = readl(®->core.ghwcfg3); |
| 97 | /* |
| 98 | * Reserve 2 spaces for the status entries of received packets |
| 99 | * and 2 spaces for bulk and control OUT endpoints. Calculate how |
| 100 | * many blocks can be alloted, assume largest packet size is 512. |
Yunzhi Li | aa33609 | 2015-06-19 17:09:04 +0800 | [diff] [blame] | 101 | * 16 locations reserved for periodic TX . |
huang lin | 8b52c93 | 2014-12-04 18:25:47 +0800 | [diff] [blame] | 102 | */ |
Yunzhi Li | aa33609 | 2015-06-19 17:09:04 +0800 | [diff] [blame] | 103 | fifo_blocks = (hwcfg3.dfifodepth - 4 - 16) / (512 / 4); |
huang lin | 8b52c93 | 2014-12-04 18:25:47 +0800 | [diff] [blame] | 104 | tx_blocks = fifo_blocks / 2; |
| 105 | |
| 106 | grxfsiz.rxfdep = (fifo_blocks - tx_blocks) * (512 / 4) + 4; |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 107 | writel(grxfsiz.d32, ®->core.grxfsiz); |
Yunzhi Li | aa33609 | 2015-06-19 17:09:04 +0800 | [diff] [blame] | 108 | gnptxfsiz.txfstaddr = grxfsiz.rxfdep; |
| 109 | gnptxfsiz.txfdep = tx_blocks * (512 / 4); |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 110 | writel(gnptxfsiz.d32, ®->core.gnptxfsiz); |
Yunzhi Li | aa33609 | 2015-06-19 17:09:04 +0800 | [diff] [blame] | 111 | hptxfsiz.txfstaddr = gnptxfsiz.txfstaddr + gnptxfsiz.txfdep; |
| 112 | hptxfsiz.txfdep = 16; |
| 113 | writel(hptxfsiz.d32, ®->core.hptxfsiz); |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 114 | |
| 115 | /* Init host channels */ |
| 116 | hcintmsk.xfercomp = 1; |
| 117 | hcintmsk.xacterr = 1; |
| 118 | hcintmsk.stall = 1; |
| 119 | hcintmsk.chhltd = 1; |
| 120 | hcintmsk.bblerr = 1; |
| 121 | for (i = 0; i < MAX_EPS_CHANNELS; i++) |
| 122 | writel(hcintmsk.d32, ®->host.hchn[i].hcintmaskn); |
| 123 | |
| 124 | /* Unmask interrupt and configure DMA mode */ |
| 125 | gahbcfg.glblintrmsk = 1; |
| 126 | gahbcfg.hbstlen = DMA_BURST_INCR8; |
| 127 | gahbcfg.dmaen = 1; |
| 128 | writel(gahbcfg.d32, ®->core.gahbcfg); |
| 129 | |
| 130 | DWC2_INST(controller)->hprt0 = ®->host.hprt; |
| 131 | |
| 132 | usb_debug("DWC2 init finished!\n"); |
| 133 | } |
| 134 | |
| 135 | static void dwc2_shutdown(hci_t *controller) |
| 136 | { |
| 137 | detach_controller(controller); |
| 138 | free(DWC2_INST(controller)->dma_buffer); |
| 139 | free(DWC2_INST(controller)); |
| 140 | free(controller); |
| 141 | } |
| 142 | |
Yunzhi Li | 4938426 | 2015-08-11 17:58:14 +0800 | [diff] [blame^] | 143 | /* Test root port device connect status */ |
| 144 | static int dwc2_disconnected(hci_t *controller) |
| 145 | { |
| 146 | dwc2_reg_t *reg = DWC2_REG(controller); |
| 147 | hprt_t hprt; |
| 148 | |
| 149 | hprt.d32 = readl(®->host.hprt); |
| 150 | return !(hprt.prtena && hprt.prtconnsts); |
| 151 | } |
| 152 | |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 153 | /* |
| 154 | * This function returns the actual transfer length when the transfer succeeded |
| 155 | * or an error code if the transfer failed |
| 156 | */ |
| 157 | static int |
| 158 | wait_for_complete(endpoint_t *ep, uint32_t ch_num) |
| 159 | { |
| 160 | hcint_t hcint; |
| 161 | hcchar_t hcchar; |
| 162 | hctsiz_t hctsiz; |
| 163 | dwc2_reg_t *reg = DWC2_REG(ep->dev->controller); |
| 164 | int timeout = 600000; /* time out after 600000 * 5us == 3s */ |
| 165 | |
| 166 | /* |
| 167 | * TODO: We should take care of up to three times of transfer error |
| 168 | * retry here, according to the USB 2.0 spec 4.5.2 |
| 169 | */ |
| 170 | do { |
| 171 | udelay(5); |
| 172 | hcint.d32 = readl(®->host.hchn[ch_num].hcintn); |
| 173 | hctsiz.d32 = readl(®->host.hchn[ch_num].hctsizn); |
| 174 | |
| 175 | if (hcint.chhltd) { |
| 176 | writel(hcint.d32, ®->host.hchn[ch_num].hcintn); |
Yunzhi Li | ebd3da7 | 2015-07-02 15:28:11 +0800 | [diff] [blame] | 177 | if (hcint.xfercomp || hcint.ack) |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 178 | return hctsiz.xfersize; |
Yunzhi Li | aa33609 | 2015-06-19 17:09:04 +0800 | [diff] [blame] | 179 | else if (hcint.nak || hcint.frmovrun) |
Yunzhi Li | ebd3da7 | 2015-07-02 15:28:11 +0800 | [diff] [blame] | 180 | return -HCSTAT_NAK; |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 181 | else if (hcint.xacterr) |
| 182 | return -HCSTAT_XFERERR; |
| 183 | else if (hcint.bblerr) |
| 184 | return -HCSTAT_BABBLE; |
| 185 | else if (hcint.stall) |
| 186 | return -HCSTAT_STALL; |
Yunzhi Li | ebd3da7 | 2015-07-02 15:28:11 +0800 | [diff] [blame] | 187 | else if (hcint.nyet) |
| 188 | return -HCSTAT_NYET; |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 189 | else |
| 190 | return -HCSTAT_UNKNOW; |
| 191 | } |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 192 | |
Yunzhi Li | 4938426 | 2015-08-11 17:58:14 +0800 | [diff] [blame^] | 193 | if (dwc2_disconnected(ep->dev->controller)) |
| 194 | return -HCSTAT_DISCONNECTED; |
| 195 | } while (timeout--); |
| 196 | /* Release the channel when hit timeout condition */ |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 197 | hcchar.d32 = readl(®->host.hchn[ch_num].hccharn); |
| 198 | if (hcchar.chen) { |
| 199 | /* |
| 200 | * Programming the HCCHARn register with the chdis and |
| 201 | * chena bits set to 1 at the same time to disable the |
| 202 | * channel and the core will generate a channel halted |
| 203 | * interrupt. |
| 204 | */ |
| 205 | hcchar.chdis = 1; |
| 206 | writel(hcchar.d32, ®->host.hchn[ch_num].hccharn); |
| 207 | do { |
| 208 | hcchar.d32 = readl(®->host.hchn[ch_num].hccharn); |
| 209 | } while (hcchar.chen); |
| 210 | |
| 211 | } |
| 212 | |
| 213 | /* Clear all pending interrupt flags */ |
| 214 | hcint.d32 = ~0; |
| 215 | writel(hcint.d32, ®->host.hchn[ch_num].hcintn); |
| 216 | |
| 217 | return -HCSTAT_TIMEOUT; |
| 218 | } |
| 219 | |
| 220 | static int |
Yunzhi Li | ebd3da7 | 2015-07-02 15:28:11 +0800 | [diff] [blame] | 221 | dwc2_do_xfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, |
Yunzhi Li | 8b49889 | 2015-07-24 16:12:42 +0800 | [diff] [blame] | 222 | uint32_t ch_num, u8 *data_buf, int *short_pkt) |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 223 | { |
| 224 | uint32_t do_copy; |
| 225 | int ret; |
| 226 | uint32_t packet_cnt; |
| 227 | uint32_t packet_size; |
| 228 | uint32_t transferred = 0; |
| 229 | uint32_t inpkt_length; |
| 230 | hctsiz_t hctsiz = { .d32 = 0 }; |
| 231 | hcchar_t hcchar = { .d32 = 0 }; |
| 232 | void *aligned_buf; |
| 233 | dwc2_reg_t *reg = DWC2_REG(ep->dev->controller); |
| 234 | |
| 235 | packet_size = ep->maxpacketsize; |
| 236 | packet_cnt = ALIGN_UP(size, packet_size) / packet_size; |
| 237 | inpkt_length = packet_cnt * packet_size; |
| 238 | /* At least 1 packet should be programed */ |
| 239 | packet_cnt = (packet_cnt == 0) ? 1 : packet_cnt; |
| 240 | |
| 241 | /* |
| 242 | * For an IN, this field is the buffer size that the application has |
| 243 | * reserved for the transfer. The application should program this field |
| 244 | * as integer multiple of the maximum packet size for IN transactions. |
| 245 | */ |
| 246 | hctsiz.xfersize = (dir == EPDIR_OUT) ? size : inpkt_length; |
| 247 | hctsiz.pktcnt = packet_cnt; |
| 248 | hctsiz.pid = pid; |
| 249 | |
| 250 | hcchar.mps = packet_size; |
| 251 | hcchar.epnum = ep->endpoint & 0xf; |
| 252 | hcchar.epdir = dir; |
| 253 | hcchar.eptype = ep->type; |
| 254 | hcchar.multicnt = 1; |
| 255 | hcchar.devaddr = ep->dev->address; |
| 256 | hcchar.chdis = 0; |
| 257 | hcchar.chen = 1; |
Yunzhi Li | ebd3da7 | 2015-07-02 15:28:11 +0800 | [diff] [blame] | 258 | if (ep->dev->speed == LOW_SPEED) |
| 259 | hcchar.lspddev = 1; |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 260 | |
| 261 | if (size > DMA_SIZE) { |
| 262 | usb_debug("Transfer too large: %d\n", size); |
| 263 | return -1; |
| 264 | } |
| 265 | |
| 266 | /* |
| 267 | * Check the buffer address which should be 4-byte aligned and DMA |
| 268 | * coherent |
| 269 | */ |
| 270 | do_copy = !dma_coherent(data_buf) || ((uintptr_t)data_buf & 0x3); |
| 271 | aligned_buf = do_copy ? DWC2_INST(ep->dev->controller)->dma_buffer : |
| 272 | data_buf; |
| 273 | |
| 274 | if (do_copy && (dir == EPDIR_OUT)) |
| 275 | memcpy(aligned_buf, data_buf, size); |
| 276 | |
| 277 | writel(hctsiz.d32, ®->host.hchn[ch_num].hctsizn); |
Ionela Voinescu | fa14385 | 2015-02-02 15:35:44 +0000 | [diff] [blame] | 278 | writel((uint32_t)virt_to_bus(aligned_buf), |
| 279 | ®->host.hchn[ch_num].hcdman); |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 280 | writel(hcchar.d32, ®->host.hchn[ch_num].hccharn); |
| 281 | |
| 282 | ret = wait_for_complete(ep, ch_num); |
| 283 | |
| 284 | if (ret >= 0) { |
| 285 | /* Calculate actual transferred length */ |
| 286 | transferred = (dir == EPDIR_IN) ? inpkt_length - ret : ret; |
| 287 | |
| 288 | if (do_copy && (dir == EPDIR_IN)) |
| 289 | memcpy(data_buf, aligned_buf, transferred); |
Yunzhi Li | 8b49889 | 2015-07-24 16:12:42 +0800 | [diff] [blame] | 290 | |
| 291 | if ((short_pkt != NULL) && (dir == EPDIR_IN)) |
| 292 | *short_pkt = (ret > 0) ? 1 : 0; |
| 293 | |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 294 | } |
| 295 | |
| 296 | /* Save data toggle */ |
| 297 | hctsiz.d32 = readl(®->host.hchn[ch_num].hctsizn); |
| 298 | ep->toggle = hctsiz.pid; |
| 299 | |
| 300 | if (ret < 0) { |
| 301 | usb_debug("%s Transfer stop code: %x\n", __func__, ret); |
| 302 | return ret; |
| 303 | } |
| 304 | return transferred; |
| 305 | } |
| 306 | |
| 307 | static int |
Yunzhi Li | ebd3da7 | 2015-07-02 15:28:11 +0800 | [diff] [blame] | 308 | dwc2_split_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, |
Yunzhi Li | 8b49889 | 2015-07-24 16:12:42 +0800 | [diff] [blame] | 309 | uint32_t ch_num, u8 *data_buf, split_info_t *split, |
| 310 | int *short_pkt) |
Yunzhi Li | ebd3da7 | 2015-07-02 15:28:11 +0800 | [diff] [blame] | 311 | { |
| 312 | dwc2_reg_t *reg = DWC2_REG(ep->dev->controller); |
| 313 | hfnum_t hfnum; |
| 314 | hcsplit_t hcsplit = { .d32 = 0 }; |
| 315 | int ret, transferred = 0; |
| 316 | |
| 317 | hcsplit.hubaddr = split->hubaddr; |
| 318 | hcsplit.prtaddr = split->hubport; |
| 319 | hcsplit.spltena = 1; |
| 320 | writel(hcsplit.d32, ®->host.hchn[ch_num].hcspltn); |
| 321 | |
| 322 | /* Wait for next frame boundary */ |
| 323 | do { |
| 324 | hfnum.d32 = readl(®->host.hfnum); |
Yunzhi Li | 4938426 | 2015-08-11 17:58:14 +0800 | [diff] [blame^] | 325 | |
| 326 | if (dwc2_disconnected(ep->dev->controller)) |
| 327 | return -HCSTAT_DISCONNECTED; |
Yunzhi Li | ebd3da7 | 2015-07-02 15:28:11 +0800 | [diff] [blame] | 328 | } while (hfnum.frnum % 8 != 0); |
| 329 | |
| 330 | /* Handle Start-Split */ |
| 331 | ret = dwc2_do_xfer(ep, dir == EPDIR_IN ? 0 : size, pid, dir, ch_num, |
Yunzhi Li | 8b49889 | 2015-07-24 16:12:42 +0800 | [diff] [blame] | 332 | data_buf, NULL); |
Yunzhi Li | ebd3da7 | 2015-07-02 15:28:11 +0800 | [diff] [blame] | 333 | if (ret < 0) |
| 334 | goto out; |
| 335 | |
| 336 | hcsplit.spltena = 1; |
| 337 | hcsplit.compsplt = 1; |
| 338 | writel(hcsplit.d32, ®->host.hchn[ch_num].hcspltn); |
| 339 | ep->toggle = pid; |
| 340 | |
| 341 | if (dir == EPDIR_OUT) |
| 342 | transferred += ret; |
| 343 | |
| 344 | /* Handle Complete-Split */ |
| 345 | do { |
| 346 | ret = dwc2_do_xfer(ep, dir == EPDIR_OUT ? 0 : size, ep->toggle, |
Yunzhi Li | 8b49889 | 2015-07-24 16:12:42 +0800 | [diff] [blame] | 347 | dir, ch_num, data_buf, short_pkt); |
Yunzhi Li | ebd3da7 | 2015-07-02 15:28:11 +0800 | [diff] [blame] | 348 | } while (ret == -HCSTAT_NYET); |
| 349 | |
| 350 | if (dir == EPDIR_IN) |
| 351 | transferred += ret; |
| 352 | |
| 353 | out: |
| 354 | /* Clear hcsplit reg */ |
| 355 | hcsplit.spltena = 0; |
| 356 | hcsplit.compsplt = 0; |
| 357 | writel(hcsplit.d32, ®->host.hchn[ch_num].hcspltn); |
| 358 | |
| 359 | if (ret < 0) |
| 360 | return ret; |
| 361 | |
| 362 | return transferred; |
| 363 | } |
| 364 | |
| 365 | static int dwc2_need_split(usbdev_t *dev, split_info_t *split) |
| 366 | { |
| 367 | if (dev->speed == HIGH_SPEED) |
| 368 | return 0; |
| 369 | |
| 370 | if (closest_usb2_hub(dev, &split->hubaddr, &split->hubport)) |
| 371 | return 0; |
| 372 | |
| 373 | return 1; |
| 374 | } |
| 375 | |
| 376 | static int |
| 377 | dwc2_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, uint32_t ch_num, |
| 378 | u8 *src, uint8_t skip_nak) |
| 379 | { |
| 380 | split_info_t split; |
Yunzhi Li | 8b49889 | 2015-07-24 16:12:42 +0800 | [diff] [blame] | 381 | int ret, short_pkt, transferred = 0, timeout = 3000; |
Yunzhi Li | ebd3da7 | 2015-07-02 15:28:11 +0800 | [diff] [blame] | 382 | |
| 383 | ep->toggle = pid; |
| 384 | |
| 385 | do { |
Yunzhi Li | 8b49889 | 2015-07-24 16:12:42 +0800 | [diff] [blame] | 386 | short_pkt = 0; |
Yunzhi Li | ebd3da7 | 2015-07-02 15:28:11 +0800 | [diff] [blame] | 387 | if (dwc2_need_split(ep->dev, &split)) { |
| 388 | nak_retry: |
Yunzhi Li | 8b49889 | 2015-07-24 16:12:42 +0800 | [diff] [blame] | 389 | ret = dwc2_split_transfer(ep, MIN(ep->maxpacketsize, |
| 390 | size), ep->toggle, dir, 0, src, &split, |
| 391 | &short_pkt); |
Yunzhi Li | ebd3da7 | 2015-07-02 15:28:11 +0800 | [diff] [blame] | 392 | |
| 393 | /* |
| 394 | * dwc2_split_transfer() waits for the next FullSpeed |
| 395 | * frame boundary, so we have one try per millisecond. |
| 396 | * It's 3s timeout for each split transfer. |
| 397 | */ |
| 398 | if (ret == -HCSTAT_NAK && !skip_nak && --timeout) { |
| 399 | udelay(500); |
| 400 | goto nak_retry; |
| 401 | } |
| 402 | } else { |
Yunzhi Li | 8b49889 | 2015-07-24 16:12:42 +0800 | [diff] [blame] | 403 | ret = dwc2_do_xfer(ep, MIN(DMA_SIZE, size), pid, dir, 0, |
| 404 | src, &short_pkt); |
Yunzhi Li | ebd3da7 | 2015-07-02 15:28:11 +0800 | [diff] [blame] | 405 | } |
| 406 | |
| 407 | if (ret < 0) |
| 408 | return ret; |
| 409 | |
| 410 | size -= ret; |
| 411 | src += ret; |
| 412 | transferred += ret; |
Yunzhi Li | 8b49889 | 2015-07-24 16:12:42 +0800 | [diff] [blame] | 413 | |
| 414 | } while (size > 0 && !short_pkt); |
Yunzhi Li | ebd3da7 | 2015-07-02 15:28:11 +0800 | [diff] [blame] | 415 | |
| 416 | return transferred; |
| 417 | } |
| 418 | |
| 419 | static int |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 420 | dwc2_bulk(endpoint_t *ep, int size, u8 *src, int finalize) |
| 421 | { |
| 422 | ep_dir_t data_dir; |
| 423 | |
| 424 | if (ep->direction == IN) |
| 425 | data_dir = EPDIR_IN; |
| 426 | else if (ep->direction == OUT) |
| 427 | data_dir = EPDIR_OUT; |
| 428 | else |
| 429 | return -1; |
| 430 | |
Yunzhi Li | ebd3da7 | 2015-07-02 15:28:11 +0800 | [diff] [blame] | 431 | return dwc2_transfer(ep, size, ep->toggle, data_dir, 0, src, 0); |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 432 | } |
| 433 | |
| 434 | static int |
| 435 | dwc2_control(usbdev_t *dev, direction_t dir, int drlen, void *setup, |
| 436 | int dalen, u8 *src) |
| 437 | { |
| 438 | int ret = 0; |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 439 | ep_dir_t data_dir; |
Yunzhi Li | ebd3da7 | 2015-07-02 15:28:11 +0800 | [diff] [blame] | 440 | endpoint_t *ep = &dev->endpoints[0]; |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 441 | |
| 442 | if (dir == IN) |
| 443 | data_dir = EPDIR_IN; |
| 444 | else if (dir == OUT) |
| 445 | data_dir = EPDIR_OUT; |
| 446 | else |
| 447 | return -1; |
| 448 | |
| 449 | /* Setup Phase */ |
Yunzhi Li | ebd3da7 | 2015-07-02 15:28:11 +0800 | [diff] [blame] | 450 | if (dwc2_transfer(ep, drlen, PID_SETUP, EPDIR_OUT, 0, setup, 0) < 0) |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 451 | return -1; |
Yunzhi Li | ebd3da7 | 2015-07-02 15:28:11 +0800 | [diff] [blame] | 452 | |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 453 | /* Data Phase */ |
Yunzhi Li | ebd3da7 | 2015-07-02 15:28:11 +0800 | [diff] [blame] | 454 | ep->toggle = PID_DATA1; |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 455 | if (dalen > 0) { |
Yunzhi Li | ebd3da7 | 2015-07-02 15:28:11 +0800 | [diff] [blame] | 456 | ret = dwc2_transfer(ep, dalen, ep->toggle, data_dir, 0, src, 0); |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 457 | if (ret < 0) |
| 458 | return -1; |
| 459 | } |
Yunzhi Li | ebd3da7 | 2015-07-02 15:28:11 +0800 | [diff] [blame] | 460 | |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 461 | /* Status Phase */ |
Yunzhi Li | ebd3da7 | 2015-07-02 15:28:11 +0800 | [diff] [blame] | 462 | if (dwc2_transfer(ep, 0, PID_DATA1, !data_dir, 0, NULL, 0) < 0) |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 463 | return -1; |
| 464 | |
| 465 | return ret; |
| 466 | } |
| 467 | |
Yunzhi Li | aa33609 | 2015-06-19 17:09:04 +0800 | [diff] [blame] | 468 | static int |
| 469 | dwc2_intr(endpoint_t *ep, int size, u8 *src) |
| 470 | { |
| 471 | ep_dir_t data_dir; |
| 472 | |
| 473 | if (ep->direction == IN) |
| 474 | data_dir = EPDIR_IN; |
| 475 | else if (ep->direction == OUT) |
| 476 | data_dir = EPDIR_OUT; |
| 477 | else |
| 478 | return -1; |
| 479 | |
Yunzhi Li | ebd3da7 | 2015-07-02 15:28:11 +0800 | [diff] [blame] | 480 | return dwc2_transfer(ep, size, ep->toggle, data_dir, 0, src, 1); |
Yunzhi Li | aa33609 | 2015-06-19 17:09:04 +0800 | [diff] [blame] | 481 | } |
| 482 | |
| 483 | static u32 dwc2_intr_get_timestamp(intr_queue_t *q) |
| 484 | { |
| 485 | hprt_t hprt; |
| 486 | hfnum_t hfnum; |
| 487 | hci_t *controller = q->endp->dev->controller; |
| 488 | dwc_ctrl_t *dwc2 = DWC2_INST(controller); |
| 489 | dwc2_reg_t *reg = DWC2_REG(controller); |
| 490 | |
| 491 | hfnum.d32 = readl(®->host.hfnum); |
| 492 | hprt.d32 = readl(dwc2->hprt0); |
| 493 | |
| 494 | /* |
| 495 | * hfnum.frnum increments when a new SOF is transmitted on |
| 496 | * the USB, and is reset to 0 when it reaches 16'h3FFF |
| 497 | */ |
| 498 | switch (hprt.prtspd) { |
| 499 | case PRTSPD_HIGH: |
| 500 | /* 8 micro-frame per ms for high-speed */ |
| 501 | return hfnum.frnum / 8; |
| 502 | case PRTSPD_FULL: |
| 503 | case PRTSPD_LOW: |
| 504 | default: |
| 505 | /* 1 micro-frame per ms for high-speed */ |
| 506 | return hfnum.frnum / 1; |
| 507 | } |
| 508 | } |
| 509 | |
| 510 | /* create and hook-up an intr queue into device schedule */ |
| 511 | static void * |
| 512 | dwc2_create_intr_queue(endpoint_t *ep, const int reqsize, |
| 513 | const int reqcount, const int reqtiming) |
| 514 | { |
| 515 | intr_queue_t *q = (intr_queue_t *)xzalloc(sizeof(intr_queue_t)); |
| 516 | |
| 517 | q->data = dma_memalign(4, reqsize); |
| 518 | q->endp = ep; |
| 519 | q->reqsize = reqsize; |
| 520 | q->reqtiming = reqtiming; |
| 521 | |
| 522 | return q; |
| 523 | } |
| 524 | |
| 525 | static void |
| 526 | dwc2_destroy_intr_queue(endpoint_t *ep, void *_q) |
| 527 | { |
| 528 | intr_queue_t *q = (intr_queue_t *)_q; |
| 529 | |
| 530 | free(q->data); |
| 531 | free(q); |
| 532 | } |
| 533 | |
| 534 | /* |
| 535 | * read one intr-packet from queue, if available. extend the queue for |
| 536 | * new input. Return NULL if nothing new available. |
| 537 | * Recommended use: while (data=poll_intr_queue(q)) process(data); |
| 538 | */ |
| 539 | static u8 * |
| 540 | dwc2_poll_intr_queue(void *_q) |
| 541 | { |
| 542 | intr_queue_t *q = (intr_queue_t *)_q; |
| 543 | int ret = 0; |
| 544 | u32 timestamp = dwc2_intr_get_timestamp(q); |
| 545 | |
| 546 | /* |
| 547 | * If hfnum.frnum run overflow it will schedule |
| 548 | * an interrupt transfer immediately |
| 549 | */ |
| 550 | if (timestamp - q->timestamp < q->reqtiming) |
| 551 | return NULL; |
| 552 | |
| 553 | q->timestamp = timestamp; |
| 554 | |
| 555 | ret = dwc2_intr(q->endp, q->reqsize, q->data); |
| 556 | |
| 557 | if (ret > 0) |
| 558 | return q->data; |
| 559 | else |
| 560 | return NULL; |
| 561 | } |
| 562 | |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 563 | hci_t *dwc2_init(void *bar) |
| 564 | { |
| 565 | hci_t *controller = new_controller(); |
| 566 | controller->instance = xzalloc(sizeof(dwc_ctrl_t)); |
| 567 | |
| 568 | DWC2_INST(controller)->dma_buffer = dma_malloc(DMA_SIZE); |
| 569 | if (!DWC2_INST(controller)->dma_buffer) { |
| 570 | usb_debug("Not enough DMA memory for DWC2 bounce buffer\n"); |
| 571 | goto free_dwc2; |
| 572 | } |
| 573 | |
| 574 | controller->type = DWC2; |
| 575 | controller->start = dummy; |
| 576 | controller->stop = dummy; |
| 577 | controller->reset = dummy; |
| 578 | controller->init = dwc2_reinit; |
| 579 | controller->shutdown = dwc2_shutdown; |
| 580 | controller->bulk = dwc2_bulk; |
| 581 | controller->control = dwc2_control; |
| 582 | controller->set_address = generic_set_address; |
| 583 | controller->finish_device_config = NULL; |
| 584 | controller->destroy_device = NULL; |
Yunzhi Li | aa33609 | 2015-06-19 17:09:04 +0800 | [diff] [blame] | 585 | controller->create_intr_queue = dwc2_create_intr_queue; |
| 586 | controller->destroy_intr_queue = dwc2_destroy_intr_queue; |
| 587 | controller->poll_intr_queue = dwc2_poll_intr_queue; |
huang lin | 365250e | 2014-08-06 16:43:43 +0800 | [diff] [blame] | 588 | controller->reg_base = (uintptr_t)bar; |
| 589 | init_device_entry(controller, 0); |
| 590 | |
| 591 | /* Init controller */ |
| 592 | controller->init(controller); |
| 593 | |
| 594 | /* Setup up root hub */ |
| 595 | controller->devices[0]->controller = controller; |
| 596 | controller->devices[0]->init = dwc2_rh_init; |
| 597 | controller->devices[0]->init(controller->devices[0]); |
| 598 | return controller; |
| 599 | |
| 600 | free_dwc2: |
| 601 | detach_controller(controller); |
| 602 | free(DWC2_INST(controller)); |
| 603 | free(controller); |
| 604 | return NULL; |
| 605 | } |