Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2004 Ron G. Minnich |
| 5 | * Copyright (C) 2004 Eric Biederman |
| 6 | * Copyright (C) 2008-2009 coresystems GmbH |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; version 2 of |
| 11 | * the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 21 | */ |
| 22 | |
Stefan Reinauer | 138be83 | 2010-02-27 01:50:21 +0000 | [diff] [blame] | 23 | /* the problem: we have 82801dbm support in fb1, and 82801er in fb2. |
| 24 | * fb1 code is what we want, fb2 structure is needed however. |
| 25 | * so we need to get fb1 code for 82801dbm into fb2 structure. |
| 26 | */ |
| 27 | /* What I did: took the 80801er stuff from fb2, verify it against the |
| 28 | * db stuff in fb1, and made sure it was right. |
| 29 | */ |
| 30 | |
| 31 | #ifndef I82801DX_H |
| 32 | #define I82801DX_H |
| 33 | |
| 34 | #if !defined( __ROMCC__ ) && !defined(__PRE_RAM__) |
| 35 | #include "chip.h" |
| 36 | extern void i82801dx_enable(device_t dev); |
| 37 | #endif |
| 38 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame^] | 39 | #define IO_APIC_ADDR 0xfec00000 |
| 40 | #define HPET_ADDR 0xfed00000 |
| 41 | |
Stefan Reinauer | bd11298 | 2010-03-17 03:14:54 +0000 | [diff] [blame] | 42 | #define DEBUG_PERIODIC_SMIS 0 |
| 43 | |
Stefan Reinauer | 138be83 | 2010-02-27 01:50:21 +0000 | [diff] [blame] | 44 | #define MAINBOARD_POWER_OFF 0 |
| 45 | #define MAINBOARD_POWER_ON 1 |
| 46 | #define MAINBOARD_POWER_KEEP 2 |
| 47 | |
| 48 | #ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL |
| 49 | #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON |
| 50 | #endif |
| 51 | |
| 52 | /* |
Stefan Reinauer | 8702ab5 | 2010-03-14 17:01:08 +0000 | [diff] [blame] | 53 | * 000 = Non-combined. P0 is primary master. P1 is secondary master. |
| 54 | * 001 = Non-combined. P0 is secondary master. P1 is primary master. |
| 55 | * 100 = Combined. P0 is primary master. P1 is primary slave. IDE is secondary; |
| 56 | * Primary IDE channel disabled. |
| 57 | * 101 = Combined. P0 is primary slave. P1 is primary master. IDE is secondary. |
| 58 | * 110 = Combined. IDE is primary. P0 is secondary master. P1 is secondary |
| 59 | * slave; Secondary IDE channel disabled. |
| 60 | * 111 = Combined. IDE is primary. P0 is secondary slave. P1 is secondary master. |
| 61 | */ |
| 62 | /* PCI Configuration Space (D31:F1) */ |
| 63 | #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ |
| 64 | #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ |
| 65 | |
| 66 | /* IDE_TIM bits */ |
| 67 | #define IDE_DECODE_ENABLE (1 << 15) |
| 68 | |
| 69 | |
Stefan Reinauer | 138be83 | 2010-02-27 01:50:21 +0000 | [diff] [blame] | 70 | |
| 71 | #define PCI_DMA_CFG 0x90 |
| 72 | #define SERIRQ_CNTL 0x64 |
| 73 | #define GEN_CNTL 0xd0 |
| 74 | #define GEN_STS 0xd4 |
| 75 | #define RTC_CONF 0xd8 |
| 76 | #define GEN_PMCON_3 0xa4 |
| 77 | |
| 78 | #define PCICMD 0x04 |
| 79 | #define PMBASE 0x40 |
| 80 | #define PMBASE_ADDR 0x0400 |
| 81 | #define ACPI_CNTL 0x44 |
| 82 | #define BIOS_CNTL 0x4E |
| 83 | #define GPIO_BASE 0x58 |
| 84 | #define GPIO_CNTL 0x5C |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame^] | 85 | #define GPIOBASE_ADDR 0x0500 |
| 86 | #define PIRQA_ROUT 0x60 |
| 87 | #define PIRQB_ROUT 0x61 |
| 88 | #define PIRQC_ROUT 0x62 |
| 89 | #define PIRQD_ROUT 0x63 |
| 90 | #define PIRQE_ROUT 0x68 |
| 91 | #define PIRQF_ROUT 0x69 |
| 92 | #define PIRQG_ROUT 0x6A |
| 93 | #define PIRQH_ROUT 0x6B |
Stefan Reinauer | 138be83 | 2010-02-27 01:50:21 +0000 | [diff] [blame] | 94 | #define COM_DEC 0xE0 |
| 95 | #define LPC_EN 0xE6 |
| 96 | #define FUNC_DIS 0xF2 |
| 97 | |
| 98 | /* 1e f0 244e */ |
| 99 | |
| 100 | #define CMD 0x04 |
| 101 | #define SBUS_NUM 0x19 |
| 102 | #define SUB_BUS_NUM 0x1A |
| 103 | #define SMLT 0x1B |
| 104 | #define IOBASE 0x1C |
| 105 | #define IOLIM 0x1D |
| 106 | #define MEMBASE 0x20 |
| 107 | #define MEMLIM 0x22 |
| 108 | #define CNF 0x50 |
| 109 | #define MTT 0x70 |
| 110 | #define PCI_MAST_STS 0x82 |
| 111 | |
| 112 | #define RTC_FAILED (1 <<2) |
| 113 | |
| 114 | |
| 115 | #define SMBUS_IO_BASE 0x1000 |
| 116 | |
| 117 | #define SMBHSTSTAT 0x0 |
| 118 | #define SMBHSTCTL 0x2 |
| 119 | #define SMBHSTCMD 0x3 |
| 120 | #define SMBXMITADD 0x4 |
| 121 | #define SMBHSTDAT0 0x5 |
| 122 | #define SMBHSTDAT1 0x6 |
| 123 | #define SMBBLKDAT 0x7 |
| 124 | #define SMBTRNSADD 0x9 |
| 125 | #define SMBSLVDATA 0xa |
| 126 | #define SMLINK_PIN_CTL 0xe |
| 127 | #define SMBUS_PIN_CTL 0xf |
| 128 | |
| 129 | /* Between 1-10 seconds, We should never timeout normally |
| 130 | * Longer than this is just painful when a timeout condition occurs. |
| 131 | */ |
| 132 | #define SMBUS_TIMEOUT (100*1000) |
| 133 | |
| 134 | #define PM1_STS 0x00 |
| 135 | #define WAK_STS (1 << 15) |
| 136 | #define PCIEXPWAK_STS (1 << 14) |
| 137 | #define PRBTNOR_STS (1 << 11) |
| 138 | #define RTC_STS (1 << 10) |
| 139 | #define PWRBTN_STS (1 << 8) |
| 140 | #define GBL_STS (1 << 5) |
| 141 | #define BM_STS (1 << 4) |
| 142 | #define TMROF_STS (1 << 0) |
| 143 | #define PM1_EN 0x02 |
| 144 | #define PCIEXPWAK_DIS (1 << 14) |
| 145 | #define RTC_EN (1 << 10) |
| 146 | #define PWRBTN_EN (1 << 8) |
| 147 | #define GBL_EN (1 << 5) |
| 148 | #define TMROF_EN (1 << 0) |
| 149 | #define PM1_CNT 0x04 |
| 150 | #define SLP_EN (1 << 13) |
| 151 | #define SLP_TYP (7 << 10) |
| 152 | #define GBL_RLS (1 << 2) |
| 153 | #define BM_RLD (1 << 1) |
| 154 | #define SCI_EN (1 << 0) |
| 155 | #define PM1_TMR 0x08 |
| 156 | #define PROC_CNT 0x10 |
| 157 | #define LV2 0x14 |
| 158 | #define LV3 0x15 |
| 159 | #define LV4 0x16 |
| 160 | #define PM2_CNT 0x20 // mobile only |
| 161 | #define GPE0_STS 0x28 |
| 162 | #define PME_B0_STS (1 << 13) |
| 163 | #define USB3_STS (1 << 12) |
| 164 | #define PME_STS (1 << 11) |
| 165 | #define BATLOW_STS (1 << 10) |
| 166 | #define GST_STS (1 << 9) |
| 167 | #define RI_STS (1 << 8) |
| 168 | #define SMB_WAK_STS (1 << 7) |
| 169 | #define TCOSCI_STS (1 << 6) |
| 170 | #define AC97_STS (1 << 5) |
| 171 | #define USB2_STS (1 << 4) |
| 172 | #define USB1_STS (1 << 3) |
| 173 | #define SWGPE_STS (1 << 2) |
| 174 | #define HOT_PLUG_STS (1 << 1) |
| 175 | #define THRM_STS (1 << 0) |
| 176 | #define GPE0_EN 0x2c |
| 177 | #define PME_B0_EN (1 << 13) |
| 178 | #define PME_EN (1 << 11) |
| 179 | #define SMI_EN 0x30 |
| 180 | #define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology |
| 181 | #define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic |
| 182 | #define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic |
| 183 | #define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS |
| 184 | #define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) |
| 185 | #define MCSMI_EN (1 << 11) // Trap microcontroller range access |
| 186 | #define BIOS_RLS (1 << 7) // asserts SCI on bit set |
| 187 | #define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set |
| 188 | #define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# |
| 189 | #define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# |
| 190 | #define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic |
| 191 | #define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit |
| 192 | #define EOS (1 << 1) // End of SMI (deassert SMI#) |
| 193 | #define GBL_SMI_EN (1 << 0) // SMI# generation at all? |
| 194 | #define SMI_STS 0x34 |
| 195 | #define ALT_GP_SMI_EN 0x38 |
| 196 | #define ALT_GP_SMI_STS 0x3a |
| 197 | #define GPE_CNTL 0x42 |
| 198 | #define DEVACT_STS 0x44 |
| 199 | #define SS_CNT 0x50 |
| 200 | #define C3_RES 0x54 |
| 201 | |
| 202 | #define TCOBASE 0x60 /* TCO Base Address Register */ |
| 203 | #define TCO1_CNT 0x08 /* TCO1 Control Register */ |
| 204 | |
Joseph Smith | 48f3e2b | 2010-03-17 03:37:18 +0000 | [diff] [blame^] | 205 | /* GEN_PMCON_3 bits */ |
| 206 | #define RTC_BATTERY_DEAD (1 << 2) |
| 207 | #define RTC_POWER_FAILED (1 << 1) |
| 208 | #define SLEEP_AFTER_POWER_FAIL (1 << 0) |
| 209 | |
Stefan Reinauer | 138be83 | 2010-02-27 01:50:21 +0000 | [diff] [blame] | 210 | #endif /* I82801DX_H */ |