| Stefan Reinauer | 4885daa | 2011-04-26 23:47:04 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Google Inc |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <stdint.h> |
| 21 | #include <arch/io.h> |
| 22 | #include <arch/romcc_io.h> |
| 23 | #include <uart8250.h> |
| 24 | #include <device/pci_def.h> |
| 25 | |
| 26 | #define PCIE_BRIDGE \ |
| 27 | PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_BUS, \ |
| 28 | CONFIG_OXFORD_OXPCIE_BRIDGE_DEVICE, \ |
| 29 | CONFIG_OXFORD_OXPCIE_BRIDGE_FUNCTION) |
| 30 | |
| 31 | #define OXPCIE_DEVICE \ |
| 32 | PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 0) |
| 33 | |
| 34 | void oxford_init(void) |
| 35 | { |
| 36 | u16 reg16; |
| 37 | |
| 38 | /* First we reset the secondary bus */ |
| 39 | reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL); |
| 40 | reg16 |= (1 << 6); /* SRESET */ |
| 41 | pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16); |
| 42 | |
| 43 | /* Assume we don't have to wait here forever */ |
| 44 | |
| 45 | /* Read back and clear reset bit. */ |
| 46 | reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL); |
| 47 | reg16 &= ~(1 << 6); /* SRESET */ |
| 48 | pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16); |
| 49 | |
| 50 | /* Set up subordinate bus number */ |
| 51 | pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS, 0x00); |
| 52 | pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS, 0x00); |
| 53 | pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS, |
| 54 | CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE); |
| 55 | pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS, |
| 56 | CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE); |
| 57 | |
| 58 | /* Memory window for the OXPCIe952 card */ |
| 59 | // XXX is the calculation of base and limit corect? |
| 60 | pci_write_config32(PCIE_BRIDGE, PCI_MEMORY_BASE, |
| 61 | ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS & 0xffff0000) | |
| 62 | ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS >> 16) & 0xff00))); |
| 63 | |
| 64 | /* Enable memory access through bridge */ |
| 65 | reg16 = pci_read_config16(PCIE_BRIDGE, PCI_COMMAND); |
| 66 | reg16 |= PCI_COMMAND_MEMORY; |
| 67 | pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16); |
| 68 | |
| 69 | // FIXME Add a timeout or this will hang forever if |
| 70 | // no device is in the slot. |
| 71 | u32 id = 0; |
| 72 | while ((id == 0) || (id == 0xffffffff)) |
| 73 | id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID); |
| 74 | |
| 75 | /* Setup base address on device */ |
| 76 | pci_write_config32(OXPCIE_DEVICE, PCI_BASE_ADDRESS_0, |
| 77 | CONFIG_OXFORD_OXPCIE_BASE_ADDRESS); |
| 78 | |
| 79 | /* Enable memory on device */ |
| 80 | reg16 = pci_read_config16(OXPCIE_DEVICE, PCI_COMMAND); |
| 81 | reg16 |= PCI_COMMAND_MEMORY; |
| 82 | pci_write_config16(OXPCIE_DEVICE, PCI_COMMAND, reg16); |
| 83 | |
| 84 | /* Now the UART initialization */ |
| 85 | u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; |
| 86 | |
| 87 | uart8250_mem_init(uart0_base, (4000000 / CONFIG_TTYS0_BAUD)); |
| 88 | } |
| 89 | |