Martin Roth | 87bbeac | 2022-10-06 15:52:38 -0600 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | /* |
| 4 | * These definitions are used to describe PCIe bifurcation and display physical |
| 5 | * connector types connected to the SOC. |
| 6 | */ |
| 7 | |
| 8 | /* TODO: Update for Morgana */ |
| 9 | |
| 10 | #ifndef PI_PLATFORM_DESCRIPTORS_H |
| 11 | #define PI_PLATFORM_DESCRIPTORS_H |
| 12 | |
Fred Reitberger | 4875a1f | 2022-11-16 12:51:42 -0500 | [diff] [blame^] | 13 | #include <stdint.h> |
| 14 | |
Martin Roth | 87bbeac | 2022-10-06 15:52:38 -0600 | [diff] [blame] | 15 | #define NUM_DXIO_PHY_PARAMS 6 |
| 16 | #define NUM_DXIO_PORT_PARAMS 6 |
| 17 | |
| 18 | /* Engine descriptor type */ |
| 19 | enum dxio_engine_type { |
| 20 | UNUSED_ENGINE = 0x00, // Unused descriptor |
| 21 | PCIE_ENGINE = 0x01, // PCIe port |
| 22 | USB_ENGINE = 0x02, // USB port |
| 23 | SATA_ENGINE = 0x03, // SATA |
| 24 | DP_ENGINE = 0x08, // Digital Display |
| 25 | ETHERNET_ENGINE = 0x10, // Ethernet (GBe, XGBe) |
| 26 | MAX_ENGINE // Max engine type for boundary check. |
| 27 | }; |
| 28 | |
| 29 | /* PCIe link capability/speed */ |
| 30 | enum dxio_link_speed_cap { |
| 31 | GEN_MAX = 0, // Maximum supported |
| 32 | GEN1, |
| 33 | GEN2, |
| 34 | GEN3, |
| 35 | GEN_INVALID // Max Gen for boundary check |
| 36 | }; |
| 37 | |
| 38 | /* Upstream Auto Speed Change Allowed */ |
| 39 | enum dxio_upstream_auto_speed_change { |
| 40 | SPDC_DEFAULT = 0, // Enabled for Gen2 and Gen3 |
| 41 | SPDC_DISABLED, |
| 42 | SPDC_ENABLED, |
| 43 | SPDC_INVALID |
| 44 | }; |
| 45 | |
| 46 | /* SATA ChannelType initialization */ |
| 47 | enum dxio_sata_channel_type { |
| 48 | SATA_CHANNEL_OTHER = 0, // Default Channel Type |
| 49 | SATA_CHANNEL_SHORT, // Short Trace Channel Type |
| 50 | SATA_CHANNEL_LONG // Long Trace Channel Type |
| 51 | }; |
| 52 | |
| 53 | /* CLKREQ for PCIe type descriptors */ |
| 54 | enum cpm_clk_req { |
| 55 | CLK_DISABLE = 0x00, |
| 56 | CLK_REQ0, |
| 57 | CLK_REQ1, |
| 58 | CLK_REQ2, |
| 59 | CLK_REQ3, |
Fred Reitberger | 4875a1f | 2022-11-16 12:51:42 -0500 | [diff] [blame^] | 60 | CLK_REQ4, |
Martin Roth | 87bbeac | 2022-10-06 15:52:38 -0600 | [diff] [blame] | 61 | CLK_REQ5, |
| 62 | CLK_REQ6, |
| 63 | CLK_ENABLE = 0xff, |
| 64 | }; |
| 65 | |
| 66 | /* PCIe link ASPM initialization */ |
| 67 | enum dxio_aspm_type { |
| 68 | ASPM_DISABLED = 0, // Disabled |
| 69 | ASPM_L0s, // PCIe L0s link state |
| 70 | ASPM_L1, // PCIe L1 link state |
| 71 | ASPM_L0sL1, // PCIe L0s & L1 link state |
| 72 | ASPM_MAX // Not valid value, used to verify input |
| 73 | }; |
| 74 | |
| 75 | enum dxio_port_param_type { |
| 76 | PP_DEVICE = 1, |
| 77 | PP_FUNCTION, |
| 78 | PP_PORT_PRESENT, |
| 79 | PP_LINK_SPEED_CAP, |
| 80 | PP_LINK_ASPM, |
| 81 | PP_HOTPLUG_TYPE, |
| 82 | PP_CLKREQ, |
| 83 | PP_ASPM_L1_1, |
| 84 | PP_ASPM_L1_2, |
| 85 | PP_COMPLIANCE, |
| 86 | PP_SAFE_MODE, |
| 87 | PP_CHIPSET_LINK, |
| 88 | PP_CLOCK_PM, |
| 89 | PP_CHANNELTYPE, |
| 90 | PP_TURN_OFF_UNUSED_LANES, |
| 91 | PP_APIC_GROUPMAP, |
| 92 | PP_APIC_SWIZZLE, |
| 93 | PP_APIC_BRIDGEINT, |
| 94 | PP_MASTER_PLL, |
| 95 | PP_SLOT_NUM, |
| 96 | PP_PHY_PARAM, |
| 97 | PP_ESM, |
| 98 | PP_CCIX, |
| 99 | PP_GEN3_DS_TX_PRESET, |
| 100 | PP_GEN3_DS_RX_PRESET_HINT, |
| 101 | PP_GEN3_US_TX_PRESET, |
| 102 | PP_GEN3_US_RX_PRESET_HINT, |
| 103 | PP_GEN4_DS_TX_PRESET, |
| 104 | PP_GEN4_US_TX_PRESET, |
| 105 | PP_GEN3_FIXED_PRESET, |
| 106 | PP_GEN4_FIXED_PRESET, |
| 107 | PP_PSPP_DC, |
| 108 | PP_PSPP_AC, |
| 109 | PP_GEN2_DEEMPHASIS, |
| 110 | PP_INVERT_POLARITY, |
| 111 | PP_TARGET_LINK_SPEED, |
| 112 | PP_GEN4_DLF_CAP_DISABLE, |
| 113 | PP_GEN4_DLF_EXCHG_DISABLE |
| 114 | }; |
| 115 | |
| 116 | /* DDI Aux channel */ |
| 117 | enum ddi_aux_type { |
| 118 | DDI_AUX1 = 0, |
| 119 | DDI_AUX2, |
| 120 | DDI_AUX3, |
| 121 | DDI_AUX4, |
| 122 | DDI_AUX5, |
| 123 | DDI_AUX6, |
| 124 | DDI_AUX_MAX // Not valid value, used to verify input |
| 125 | }; |
| 126 | |
| 127 | /* DDI Hdp Index */ |
| 128 | enum ddi_hdp_type { |
| 129 | DDI_HDP1 = 0, |
| 130 | DDI_HDP2, |
| 131 | DDI_HDP3, |
| 132 | DDI_HDP4, |
| 133 | DDI_HDP5, |
| 134 | DDI_HDP6, |
| 135 | DDI_HDP_MAX // Not valid value, used to verify input |
| 136 | }; |
| 137 | |
| 138 | /* DDI display connector type */ |
| 139 | enum ddi_connector_type { |
| 140 | DDI_DP = 0, // DP |
| 141 | DDI_EDP, // eDP |
| 142 | DDI_SINGLE_LINK_DVI, // Single Link DVI-D |
| 143 | DDI_DUAL_LINK_DVI, // Dual Link DVI-D |
| 144 | DDI_HDMI, // HDMI |
| 145 | DDI_DP_TO_VGA, // DP-to-VGA |
| 146 | DDI_DP_TO_LVDS, // DP-to-LVDS |
| 147 | DDI_NUTMEG_DP_TO_VGA, // Hudson-2 NutMeg DP-to-VGA |
| 148 | DDI_SINGLE_LINK_DVI_I, // Single Link DVI-I |
Fred Reitberger | 4875a1f | 2022-11-16 12:51:42 -0500 | [diff] [blame^] | 149 | DDI_DP_W_TYPEC, // DP with USB type C |
| 150 | DDI_DP_WO_TYPEC, // DP without USB type C |
Martin Roth | 87bbeac | 2022-10-06 15:52:38 -0600 | [diff] [blame] | 151 | DDI_EDP_TO_LVDS, // eDP-to-LVDS translator chip without AMD SW init |
| 152 | DDI_EDP_TO_LVDS_SW, // eDP-to-LVDS translator which requires AMD SW init |
| 153 | DDI_AUTO_DETECT, // VBIOS auto detect connector type |
| 154 | DDI_UNUSED_TYPE, // UnusedType |
| 155 | DDI_MAX_CONNECTOR_TYPE // Not valid value, used to verify input |
| 156 | }; |
| 157 | |
| 158 | /* Cezanne DDI Descriptor: used for configuring display outputs */ |
| 159 | typedef struct __packed { |
| 160 | uint8_t connector_type; // see ddi_connector_type |
| 161 | uint8_t aux_index; // see ddi_aux_type |
| 162 | uint8_t hdp_index; // see ddi_hdp_type |
| 163 | uint8_t reserved; |
| 164 | } fsp_ddi_descriptor; |
| 165 | |
| 166 | /* |
Fred Reitberger | 4875a1f | 2022-11-16 12:51:42 -0500 | [diff] [blame^] | 167 | * Morgana DXIO Descriptor: Used for assigning lanes to PCIe engines, configure |
Martin Roth | 87bbeac | 2022-10-06 15:52:38 -0600 | [diff] [blame] | 168 | * bifurcation and other settings. Beware that the lane numbers in here are the |
| 169 | * logical and not the physical lane numbers! |
| 170 | * |
Fred Reitberger | 4875a1f | 2022-11-16 12:51:42 -0500 | [diff] [blame^] | 171 | * Morgana DXIO logical lane to physical PCIe lane mapping: |
Martin Roth | 87bbeac | 2022-10-06 15:52:38 -0600 | [diff] [blame] | 172 | * |
Fred Reitberger | 4875a1f | 2022-11-16 12:51:42 -0500 | [diff] [blame^] | 173 | * logical | physical |
| 174 | * ----------|------------ |
| 175 | * PA[00:03] | GPP[03:00] |
| 176 | * PA[04:05] | GPP[08:09] |
| 177 | * PB[00:07] | GPP[12:19] |
Martin Roth | 87bbeac | 2022-10-06 15:52:38 -0600 | [diff] [blame] | 178 | * |
| 179 | * Different ports mustn't overlap or be assigned to the same lane(s). Within |
| 180 | * ports with the same width the one with a higher start logical lane number |
| 181 | * needs to be assigned to a higher PCIe root port number; ports of the same |
| 182 | * size don't have to be assigned to consecutive PCIe root ports though. |
| 183 | */ |
| 184 | typedef struct __packed { |
| 185 | uint8_t engine_type; // See dxio_engine_type |
| 186 | uint8_t start_logical_lane; // Start lane of the pci device |
| 187 | uint8_t end_logical_lane; // End lane of the pci device |
| 188 | uint8_t gpio_group_id; // GPIO number used as reset |
| 189 | uint32_t port_present :1; // Should be TRUE if train link |
Fred Reitberger | 4875a1f | 2022-11-16 12:51:42 -0500 | [diff] [blame^] | 190 | uint32_t :7; |
Martin Roth | 87bbeac | 2022-10-06 15:52:38 -0600 | [diff] [blame] | 191 | uint32_t device_number :5; // Desired root port device number |
| 192 | uint32_t function_number :3; // Desired root port function number |
| 193 | uint32_t link_speed_capability :2; // See dxio_link_speed_cap |
| 194 | uint32_t auto_spd_change :2; // See dxio_upstream_auto_speed_change |
| 195 | uint32_t eq_preset :4; // Gen3 equalization preset |
| 196 | uint32_t link_aspm :2; // See dxio_aspm_type |
| 197 | uint32_t link_aspm_L1_1 :1; // En/Dis root port capabilities for L1.1 |
| 198 | uint32_t link_aspm_L1_2 :1; // En/Dis root port capabilities for L1.2 |
| 199 | uint32_t clk_req :4; // See cpm_clk_req |
Fred Reitberger | 4875a1f | 2022-11-16 12:51:42 -0500 | [diff] [blame^] | 200 | uint8_t link_hotplug; // Hotplug control |
| 201 | uint8_t slot_power_limit; // PCIe slot power limit |
| 202 | uint32_t slot_power_limit_scale :2; // PCIe slot power limit scale |
| 203 | uint32_t :6; |
| 204 | uint32_t link_compliance_mode :1; // Force port into compliance mode |
| 205 | uint32_t link_safe_mode :1; // Safe mode capability |
| 206 | uint32_t sb_link :1; // Link type |
| 207 | uint32_t clk_pm_support :1; // Clock power management support |
Martin Roth | 87bbeac | 2022-10-06 15:52:38 -0600 | [diff] [blame] | 208 | uint32_t channel_type :3; // See dxio_sata_channel_type |
| 209 | uint32_t turn_off_unused_lanes :1; // Power down lanes if device not present |
| 210 | uint8_t reserved[4]; |
| 211 | uint8_t phy_params[NUM_DXIO_PHY_PARAMS*2]; |
| 212 | uint16_t port_params[NUM_DXIO_PORT_PARAMS*2]; // key-value parameters. see dxio_port_param_type |
| 213 | } fsp_dxio_descriptor; |
| 214 | |
| 215 | #endif /* PI_PLATFORM_DESCRIPTORS_H */ |