Angel Pons | 53e528a | 2020-04-03 01:23:03 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 2 | |
Youness Alaoui | 0e977fc | 2017-05-25 14:48:18 -0500 | [diff] [blame] | 3 | #include <assert.h> |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 4 | #include <soc/romstage.h> |
Youness Alaoui | 0e977fc | 2017-05-25 14:48:18 -0500 | [diff] [blame] | 5 | #include <spd_bin.h> |
Angel Pons | 42aa2cb | 2020-10-09 23:24:31 +0200 | [diff] [blame] | 6 | #include <stdint.h> |
Nico Huber | 0ebdf2a | 2019-05-04 17:06:06 +0200 | [diff] [blame] | 7 | #include <string.h> |
| 8 | |
Matt DeVillier | fb1cd09 | 2017-06-22 15:54:07 -0400 | [diff] [blame] | 9 | void mainboard_memory_init_params(FSPM_UPD *mupd) |
Youness Alaoui | 047475c | 2017-05-08 16:50:23 -0400 | [diff] [blame] | 10 | { |
Angel Pons | 42aa2cb | 2020-10-09 23:24:31 +0200 | [diff] [blame] | 11 | const u16 rcomp_resistors[3] = { 121, 81, 100 }; |
| 12 | |
| 13 | const u16 rcomp_targets[5] = { 100, 40, 20, 20, 26 }; |
| 14 | |
| 15 | FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; |
| 16 | |
Youness Alaoui | 0e977fc | 2017-05-25 14:48:18 -0500 | [diff] [blame] | 17 | struct spd_block blk = { |
Nico Huber | 5f9c673 | 2017-06-28 16:42:51 +0200 | [diff] [blame] | 18 | .addr_map = { 0x50 }, |
Youness Alaoui | 0e977fc | 2017-05-25 14:48:18 -0500 | [diff] [blame] | 19 | }; |
| 20 | |
Angel Pons | 42aa2cb | 2020-10-09 23:24:31 +0200 | [diff] [blame] | 21 | assert(sizeof(mem_cfg->RcompResistor) == sizeof(rcomp_resistors)); |
| 22 | assert(sizeof(mem_cfg->RcompTarget) == sizeof(rcomp_targets)); |
Matt DeVillier | fb1cd09 | 2017-06-22 15:54:07 -0400 | [diff] [blame] | 23 | |
Youness Alaoui | 0e977fc | 2017-05-25 14:48:18 -0500 | [diff] [blame] | 24 | get_spd_smbus(&blk); |
| 25 | dump_spd_info(&blk); |
Youness Alaoui | 0e977fc | 2017-05-25 14:48:18 -0500 | [diff] [blame] | 26 | assert(blk.spd_array[0][0] != 0); |
Youness Alaoui | 3d60718 | 2017-06-15 16:50:47 -0400 | [diff] [blame] | 27 | |
Angel Pons | 42aa2cb | 2020-10-09 23:24:31 +0200 | [diff] [blame] | 28 | memcpy(mem_cfg->RcompResistor, rcomp_resistors, sizeof(mem_cfg->RcompResistor)); |
| 29 | memcpy(mem_cfg->RcompTarget, rcomp_targets, sizeof(mem_cfg->RcompTarget)); |
Youness Alaoui | 0e977fc | 2017-05-25 14:48:18 -0500 | [diff] [blame] | 30 | |
Matt DeVillier | fb1cd09 | 2017-06-22 15:54:07 -0400 | [diff] [blame] | 31 | mem_cfg->DqPinsInterleaved = TRUE; |
Angel Pons | e1269a7 | 2021-08-30 11:07:05 +0200 | [diff] [blame] | 32 | mem_cfg->CaVrefConfig = 2; |
Matt DeVillier | fb1cd09 | 2017-06-22 15:54:07 -0400 | [diff] [blame] | 33 | mem_cfg->MemorySpdDataLen = blk.len; |
Elyes Haouas | 486240f | 2022-11-18 15:21:03 +0100 | [diff] [blame^] | 34 | mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; |
Matt DeVillier | b5eae28 | 2020-09-23 17:11:19 -0500 | [diff] [blame] | 35 | |
| 36 | /* Enable and set SATA HSIO adjustments for ports 0 and 2 */ |
| 37 | mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[0] = 1; |
| 38 | mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[2] = 1; |
| 39 | mem_cfg->PchSataHsioRxGen3EqBoostMag[0] = 1; |
| 40 | mem_cfg->PchSataHsioRxGen3EqBoostMag[2] = 1; |
Youness Alaoui | 0e977fc | 2017-05-25 14:48:18 -0500 | [diff] [blame] | 41 | } |