Michał Żygowski | 83565de | 2019-03-27 11:35:48 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Michał Żygowski | 83565de | 2019-03-27 11:35:48 +0100 | [diff] [blame] | 2 | |
| 3 | #include <device/pci_ops.h> |
| 4 | #include <soc/lpc.h> |
| 5 | #include <soc/pci_devs.h> |
| 6 | #include <soc/romstage.h> |
| 7 | #include <superio/ite/common/ite.h> |
| 8 | #include <superio/ite/it8613e/it8613e.h> |
| 9 | |
| 10 | #define SERIAL1_DEV PNP_DEV(0x2e, IT8613E_SP1) |
| 11 | |
| 12 | void mainboard_after_memory_init(void) |
| 13 | { |
| 14 | /* |
Martin Roth | 50863da | 2021-10-01 14:37:30 -0600 | [diff] [blame] | 15 | * FSP enables internal UART. Disable it and re-enable Super I/O UART to |
Michał Żygowski | 83565de | 2019-03-27 11:35:48 +0100 | [diff] [blame] | 16 | * prevent loss of debug information on serial. |
| 17 | */ |
Elyes Haouas | 486240f | 2022-11-18 15:21:03 +0100 | [diff] [blame^] | 18 | pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, (u32)0); |
Michał Żygowski | 83565de | 2019-03-27 11:35:48 +0100 | [diff] [blame] | 19 | ite_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); |
| 20 | } |
| 21 | |
| 22 | void mainboard_memory_init_params(struct romstage_params *params, |
| 23 | MEMORY_INIT_UPD *memory_params) |
| 24 | { |
| 25 | /* |
| 26 | * Set SPD and memory configuration: |
| 27 | * Memory type: 0=DimmInstalled, |
| 28 | * 1=SolderDownMemory, |
| 29 | * 2=DimmDisabled |
| 30 | */ |
| 31 | memory_params->PcdMemChannel0Config = 0; |
| 32 | memory_params->PcdMemChannel1Config = 2; |
| 33 | } |