Tim Crawford | d7a476c | 2023-03-02 09:17:59 -0700 | [diff] [blame] | 1 | chip soc/intel/alderlake |
| 2 | register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{ |
| 3 | .tdp_pl1_override = 15, |
| 4 | .tdp_pl2_override = 46, |
Tim Crawford | d7a476c | 2023-03-02 09:17:59 -0700 | [diff] [blame] | 5 | }" |
| 6 | |
| 7 | # GPE configuration |
| 8 | register "pmc_gpe0_dw0" = "PMC_GPP_A" |
| 9 | register "pmc_gpe0_dw1" = "PMC_GPP_R" |
| 10 | register "pmc_gpe0_dw2" = "PMC_GPD" |
| 11 | |
| 12 | device domain 0 on |
| 13 | subsystemid 0x1558 0x7718 inherit |
| 14 | |
| 15 | device ref pcie4_0 on |
| 16 | # PCIe PEG0 x4, Clock 0 (SSD2) |
| 17 | register "cpu_pcie_rp[CPU_RP(1)]" = "{ |
| 18 | .clk_src = 0, |
| 19 | .clk_req = 0, |
| 20 | .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| 21 | }" |
| 22 | chip soc/intel/common/block/pcie/rtd3 |
| 23 | register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_EN |
| 24 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_CPU_SSD2_RST# |
| 25 | register "srcclk_pin" = "0" # SSD0_CLKREQ# |
| 26 | device generic 0 on end |
| 27 | end |
| 28 | end |
| 29 | device ref tcss_xhci on |
| 30 | register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" |
| 31 | chip drivers/usb/acpi |
| 32 | device ref tcss_root_hub on |
| 33 | chip drivers/usb/acpi |
| 34 | register "desc" = ""TBT Type-C"" |
| 35 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 36 | device ref tcss_usb3_port1 on end |
| 37 | end |
| 38 | end |
| 39 | end |
| 40 | end |
| 41 | device ref xhci on |
| 42 | # USB2 |
| 43 | register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Left |
| 44 | register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Right |
| 45 | register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1 |
| 46 | register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # 3G/LTE |
| 47 | register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera |
| 48 | register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth |
| 49 | # USB3 |
| 50 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Left |
| 51 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Right |
| 52 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 3G/LTE |
| 53 | # ACPI |
| 54 | chip drivers/usb/acpi |
| 55 | device ref xhci_root_hub on |
| 56 | chip drivers/usb/acpi |
| 57 | register "desc" = ""USB2 Type-A Left"" |
| 58 | register "type" = "UPC_TYPE_A" |
| 59 | device ref usb2_port1 on end |
| 60 | end |
| 61 | chip drivers/usb/acpi |
| 62 | register "desc" = ""USB2 Type-A Right"" |
| 63 | register "type" = "UPC_TYPE_A" |
| 64 | device ref usb2_port2 on end |
| 65 | end |
| 66 | chip drivers/usb/acpi |
| 67 | register "desc" = ""USB2 Type-C"" |
| 68 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 69 | device ref usb2_port3 on end |
| 70 | end |
| 71 | chip drivers/usb/acpi |
| 72 | register "desc" = ""USB2 3G/LTE"" |
| 73 | register "type" = "UPC_TYPE_INTERNAL" |
| 74 | device ref usb2_port4 on end |
| 75 | end |
| 76 | chip drivers/usb/acpi |
| 77 | register "desc" = ""USB2 Camera"" |
| 78 | register "type" = "UPC_TYPE_INTERNAL" |
| 79 | device ref usb2_port7 on end |
| 80 | end |
| 81 | chip drivers/usb/acpi |
| 82 | register "desc" = ""USB2 Bluetooth"" |
| 83 | register "type" = "UPC_TYPE_INTERNAL" |
| 84 | device ref usb2_port10 on end |
| 85 | end |
| 86 | chip drivers/usb/acpi |
| 87 | register "desc" = ""USB3 Type-A Left"" |
| 88 | register "type" = "UPC_TYPE_A" |
| 89 | device ref usb3_port1 on end |
| 90 | end |
| 91 | chip drivers/usb/acpi |
| 92 | register "desc" = ""USB3 Type-A Right"" |
| 93 | register "type" = "UPC_TYPE_A" |
| 94 | device ref usb3_port2 on end |
| 95 | end |
| 96 | chip drivers/usb/acpi |
| 97 | register "desc" = ""USB3 Type-C"" |
| 98 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 99 | device ref usb3_port3 on end |
| 100 | end |
| 101 | end |
| 102 | end |
| 103 | end |
| 104 | device ref tcss_dma0 on |
| 105 | chip drivers/intel/usb4/retimer |
| 106 | register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" |
| 107 | use tcss_usb3_port1 as dfp[0].typec_port |
| 108 | device generic 0 on end |
| 109 | end |
| 110 | end |
| 111 | device ref pcie_rp5 on |
| 112 | # PCIe RP#5 x1, Clock 2 (WLAN) |
| 113 | register "pch_pcie_rp[PCH_RP(5)]" = "{ |
| 114 | .clk_src = 2, |
| 115 | .clk_req = 2, |
| 116 | .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| 117 | }" |
| 118 | chip soc/intel/common/block/pcie/rtd3 |
| 119 | register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A13)" # PCH_BT_EN |
| 120 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B17)" # WLAN_RST# |
| 121 | register "srcclk_pin" = "2" # WLAN_CLKREQ# |
| 122 | device generic 0 on end |
| 123 | end |
| 124 | end |
| 125 | device ref pcie_rp6 on |
| 126 | # PCIe RP#6 x1, Clock 6 (CARD) |
| 127 | register "pch_pcie_rp[PCH_RP(6)]" = "{ |
| 128 | .clk_src = 6, |
| 129 | .clk_req = 6, |
| 130 | .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, |
| 131 | }" |
| 132 | end |
| 133 | device ref pcie_rp9 on |
| 134 | # PCIe RP#9 x4, Clock 1 (SSD1) |
| 135 | register "pch_pcie_rp[PCH_RP(9)]" = "{ |
| 136 | .clk_src = 1, |
| 137 | .clk_req = 1, |
| 138 | .flags = PCIE_RP_LTR, |
| 139 | }" |
| 140 | chip soc/intel/common/block/pcie/rtd3 |
| 141 | register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" # SSD1_PWR_EN |
| 142 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # M2_SSD1_RST# |
| 143 | register "srcclk_pin" = "1" # SSD1_CLKREQ# |
| 144 | device generic 0 on end |
| 145 | end |
| 146 | end |
| 147 | device ref pmc hidden |
| 148 | chip drivers/intel/pmc_mux |
| 149 | device generic 0 on |
| 150 | chip drivers/intel/pmc_mux/conn |
| 151 | # J_TYPEC1 |
| 152 | use usb2_port3 as usb2_port |
| 153 | use tcss_usb3_port1 as usb3_port |
| 154 | device generic 0 alias conn0 on end |
| 155 | end |
| 156 | end |
| 157 | end |
| 158 | end |
| 159 | end |
| 160 | end |