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Angel Pons47f26db2020-04-05 13:22:34 +02001/* SPDX-License-Identifier: GPL-2.0-only */
2/* This file is part of the coreboot project. */
Matt DeVillier9be3f5d2017-01-16 17:32:38 -06003
4#ifndef VARIANT_H
5#define VARIANT_H
6
Elyes HAOUASdfbe6bd2018-10-29 06:56:52 +01007#include <stdint.h>
8
Matt DeVillier9be3f5d2017-01-16 17:32:38 -06009/*
10 * RAM_ID[2:0] are on GPIO_SSUS[39:37]
11 * 0b0000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
12 * 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
13 * 0b0010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
14 * 0b0011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz
15 * 0b0100 - 2GiB total - 2 x 1GiB Samsung K4B2G1646Q-BYK0 1600MHz
16 * 0b0101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
17 * 0b0110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
18 * 0b0111 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz
19 * 0b1000 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
20 * 0b1001 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz
21 * 0b1010 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
22 */
23
24static const uint32_t dual_channel_config =
25 (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) |
26 (1 << 4) | (1 << 6) | (1 << 7);
27
28#define SPD_SIZE 256
29#define GPIO_SSUS_37_PAD 57
30#define GPIO_SSUS_38_PAD 50
31#define GPIO_SSUS_39_PAD 58
32#define GPIO_SSUS_40_PAD 52
Matt DeVillier474a7c52017-02-07 22:07:56 -060033#define GPIO_SSUS_40_PAD_USE_PULLDOWN
Matt DeVillier9be3f5d2017-01-16 17:32:38 -060034
35#endif