chenzanxi | 8130959 | 2021-01-22 18:16:13 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include "../panel.h" |
| 4 | |
| 5 | struct panel_serializable_data STA_QFH032011_53G = { |
| 6 | .edid = { |
| 7 | .ascii_string = "QFH032011-53G", |
| 8 | .manufacturer_name = "STA", |
| 9 | .panel_bits_per_color = 8, |
| 10 | .panel_bits_per_pixel = 24, |
| 11 | .mode = { |
Sunway | 479247a | 2021-03-29 15:20:13 +0800 | [diff] [blame^] | 12 | .pixel_clock = 165731, |
chenzanxi | 8130959 | 2021-01-22 18:16:13 +0800 | [diff] [blame] | 13 | .lvds_dual_channel = 0, |
| 14 | .refresh = 60, |
| 15 | .ha = 1200, .hbl = 210, .hso = 100, .hspw = 10, |
| 16 | .va = 1920, .vbl = 39, .vso = 14, .vspw = 10, |
| 17 | .phsync = '-', .pvsync = '-', |
| 18 | .x_mm = 135, .y_mm = 217, |
| 19 | }, |
| 20 | }, |
| 21 | .orientation = LB_FB_ORIENTATION_LEFT_UP, |
| 22 | .init = { |
Sunway | 479247a | 2021-03-29 15:20:13 +0800 | [diff] [blame^] | 23 | INIT_DCS_CMD(0xB0, 0x01), |
chenzanxi | 8130959 | 2021-01-22 18:16:13 +0800 | [diff] [blame] | 24 | INIT_DCS_CMD(0xC3, 0x4F), |
| 25 | INIT_DCS_CMD(0xC4, 0x40), |
| 26 | INIT_DCS_CMD(0xC5, 0x40), |
| 27 | INIT_DCS_CMD(0xC6, 0x40), |
| 28 | INIT_DCS_CMD(0xC7, 0x40), |
| 29 | INIT_DCS_CMD(0xC8, 0x4D), |
| 30 | INIT_DCS_CMD(0xC9, 0x52), |
| 31 | INIT_DCS_CMD(0xCA, 0x51), |
| 32 | INIT_DCS_CMD(0xCD, 0x5D), |
| 33 | INIT_DCS_CMD(0xCE, 0x5B), |
| 34 | INIT_DCS_CMD(0xCF, 0x4B), |
| 35 | INIT_DCS_CMD(0xD0, 0x49), |
| 36 | INIT_DCS_CMD(0xD1, 0x47), |
| 37 | INIT_DCS_CMD(0xD2, 0x45), |
| 38 | INIT_DCS_CMD(0xD3, 0x41), |
| 39 | INIT_DCS_CMD(0xD7, 0x50), |
| 40 | INIT_DCS_CMD(0xD8, 0x40), |
| 41 | INIT_DCS_CMD(0xD9, 0x40), |
| 42 | INIT_DCS_CMD(0xDA, 0x40), |
| 43 | INIT_DCS_CMD(0xDB, 0x40), |
| 44 | INIT_DCS_CMD(0xDC, 0x4E), |
| 45 | INIT_DCS_CMD(0xDD, 0x52), |
| 46 | INIT_DCS_CMD(0xDE, 0x51), |
| 47 | INIT_DCS_CMD(0xE1, 0x5E), |
| 48 | INIT_DCS_CMD(0xE2, 0x5C), |
| 49 | INIT_DCS_CMD(0xE3, 0x4C), |
| 50 | INIT_DCS_CMD(0xE4, 0x4A), |
| 51 | INIT_DCS_CMD(0xE5, 0x48), |
| 52 | INIT_DCS_CMD(0xE6, 0x46), |
| 53 | INIT_DCS_CMD(0xE7, 0x42), |
| 54 | INIT_DCS_CMD(0xB0, 0x03), |
| 55 | INIT_DCS_CMD(0xBE, 0x03), |
| 56 | INIT_DCS_CMD(0xCC, 0x44), |
| 57 | INIT_DCS_CMD(0xC8, 0x07), |
| 58 | INIT_DCS_CMD(0xC9, 0x05), |
| 59 | INIT_DCS_CMD(0xCA, 0x42), |
| 60 | INIT_DCS_CMD(0xCD, 0x3E), |
| 61 | INIT_DCS_CMD(0xCF, 0x60), |
| 62 | INIT_DCS_CMD(0xD2, 0x04), |
| 63 | INIT_DCS_CMD(0xD3, 0x04), |
| 64 | INIT_DCS_CMD(0xD4, 0x01), |
| 65 | INIT_DCS_CMD(0xD5, 0x00), |
Sunway | 479247a | 2021-03-29 15:20:13 +0800 | [diff] [blame^] | 66 | INIT_DCS_CMD(0xD6, 0x03), |
chenzanxi | 8130959 | 2021-01-22 18:16:13 +0800 | [diff] [blame] | 67 | INIT_DCS_CMD(0xD7, 0x04), |
| 68 | INIT_DCS_CMD(0xD9, 0x01), |
| 69 | INIT_DCS_CMD(0xDB, 0x01), |
| 70 | INIT_DCS_CMD(0xE4, 0xF0), |
| 71 | INIT_DCS_CMD(0xE5, 0x0A), |
| 72 | INIT_DCS_CMD(0xB0, 0x00), |
Sunway | 479247a | 2021-03-29 15:20:13 +0800 | [diff] [blame^] | 73 | INIT_DCS_CMD(0xCC, 0x08), |
chenzanxi | 8130959 | 2021-01-22 18:16:13 +0800 | [diff] [blame] | 74 | INIT_DCS_CMD(0xC2, 0x08), |
| 75 | INIT_DCS_CMD(0xC4, 0x10), |
| 76 | INIT_DCS_CMD(0xB0, 0x02), |
| 77 | INIT_DCS_CMD(0xC0, 0x00), |
| 78 | INIT_DCS_CMD(0xC1, 0x0A), |
| 79 | INIT_DCS_CMD(0xC2, 0x20), |
| 80 | INIT_DCS_CMD(0xC3, 0x24), |
| 81 | INIT_DCS_CMD(0xC4, 0x23), |
| 82 | INIT_DCS_CMD(0xC5, 0x29), |
| 83 | INIT_DCS_CMD(0xC6, 0x23), |
| 84 | INIT_DCS_CMD(0xC7, 0x1C), |
| 85 | INIT_DCS_CMD(0xC8, 0x19), |
| 86 | INIT_DCS_CMD(0xC9, 0x17), |
| 87 | INIT_DCS_CMD(0xCA, 0x17), |
| 88 | INIT_DCS_CMD(0xCB, 0x18), |
| 89 | INIT_DCS_CMD(0xCC, 0x1A), |
| 90 | INIT_DCS_CMD(0xCD, 0x1E), |
| 91 | INIT_DCS_CMD(0xCE, 0x20), |
| 92 | INIT_DCS_CMD(0xCF, 0x23), |
| 93 | INIT_DCS_CMD(0xD0, 0x07), |
| 94 | INIT_DCS_CMD(0xD1, 0x00), |
| 95 | INIT_DCS_CMD(0xD2, 0x00), |
| 96 | INIT_DCS_CMD(0xD3, 0x0A), |
| 97 | INIT_DCS_CMD(0xD4, 0x13), |
| 98 | INIT_DCS_CMD(0xD5, 0x1C), |
| 99 | INIT_DCS_CMD(0xD6, 0x1A), |
| 100 | INIT_DCS_CMD(0xD7, 0x13), |
| 101 | INIT_DCS_CMD(0xD8, 0x17), |
| 102 | INIT_DCS_CMD(0xD9, 0x1C), |
| 103 | INIT_DCS_CMD(0xDA, 0x19), |
| 104 | INIT_DCS_CMD(0xDB, 0x17), |
| 105 | INIT_DCS_CMD(0xDC, 0x17), |
| 106 | INIT_DCS_CMD(0xDD, 0x18), |
| 107 | INIT_DCS_CMD(0xDE, 0x1A), |
| 108 | INIT_DCS_CMD(0xDF, 0x1E), |
| 109 | INIT_DCS_CMD(0xE0, 0x20), |
| 110 | INIT_DCS_CMD(0xE1, 0x23), |
| 111 | INIT_DCS_CMD(0xE2, 0x07), |
| 112 | INIT_DCS_CMD(0X11), |
| 113 | INIT_DELAY_CMD(120), |
| 114 | INIT_DCS_CMD(0X29), |
| 115 | INIT_DELAY_CMD(50), |
| 116 | INIT_END_CMD, |
| 117 | }, |
| 118 | }; |