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review.coreboot.org / coreboot / 476f7316a1e2596cc5c3e83d05003203a042a4eb / . / src / soc / qualcomm / ipq806x / clock.h
blob: 263b81b0b833fd220755e104b7ff4b3a75a4de74 [file] [log] [blame]
Vadim Bendebury476f7312014-04-08 18:45:46 -0700[diff] [blame^]1/*
2 * Copyright (c) 2012-2013 The Linux Foundation. All rights reserved.
3 * Source : APQ8064 LK Boot
4 *
5 * Copyright (c) 2012, Code Aurora Forum. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
9 * met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above
13 * copyright notice, this list of conditions and the following
14 * disclaimer in the documentation and/or other materials provided
15 * with the distribution.
16 * * Neither the name of Code Aurora Forum, Inc. nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
27 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
28 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
29 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
30 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#ifndef __PLATFORM_IPQ860X_CLOCK_H_
34#define __PLATFORM_IPQ860X_CLOCK_H_
35
36#include <asm/io.h>
37/* UART clock @ 7.3728 MHz */
38#define UART_DM_CLK_RX_TX_BIT_RATE 0xCC
39
40/* UART specific definitions */
41
42#define BIT(s) (1<<s)
43#define Uart_ns_val NS(BIT_POS_31,BIT_POS_16,N_VALUE,M_VALUE, 5, 4, 3, 1, 2, 0,3)
44#define Uart_clk_ns_mask (BM(BIT_POS_31, BIT_POS_16) | BM(BIT_POS_6, BIT_POS_0))
45#define Uart_mnd_en_mask BIT(8) * !!(625)
46#define Uart_en_mask BIT(11)
47#define MD16(m, n) (BVAL(BIT_POS_31, BIT_POS_16, m) | BVAL(BIT_POS_15, BIT_POS_0, ~(n)))
48#define Uart_ns_val_rumi NS(BIT_POS_31, BIT_POS_16, N_VALUE, M_VALUE, 5, 4, 3, 1, 2, 0,0)
49#define GSBIn_UART_APPS_MD_REG(n) REG(0x29D0+(0x20*((n)-1)))
50#define GSBIn_UART_APPS_NS_REG(n) REG(0x29D4+(0x20*((n)-1)))
51#define GSBIn_HCLK_CTL_REG(n) REG(0x29C0+(0x20*((n)-1)))
52#define BB_PLL_ENA_SC0_REG REG(0x34C0)
53#define BB_PLL8_STATUS_REG REG(0x3158)
54#define REG(off) (MSM_CLK_CTL_BASE + (off))
55#define PLL8_STATUS_BIT 16
56
57#define PLL_LOCK_DET_STATUS_REG REG(0x03420)
58#define SFAB_AHB_S3_FCLK_CTL_REG REG(0x0216C)
59#define CFPB_CLK_NS_REG REG(0x0264C)
60#define CFPB0_HCLK_CTL_REG REG(0x02650)
61#define SFAB_CFPB_S_HCLK_CTL_REG REG(0x026C0)
62#define CFPB_SPLITTER_HCLK_CTL_REG REG(0x026E0)
63#define EBI2_CLK_CTL_REG REG(0x03B00)
64
65#define ALWAYS_ON_CLK_BRANCH_ENA(i) ((i) << 8)
66
67#define CLK_BRANCH_ENA_MASK 0x00000010
68#define CLK_BRANCH_ENA_ENABLE 0x00000010
69#define CLK_BRANCH_ENA_DISABLE 0x00000000
70#define CLK_BRANCH_ENA(i) ((i) << 4)
71
72/* Register: CFPB_CLK_NS */
73#define CLK_DIV_MASK 0x00000003
74#define CLK_DIV_DIV_1 0x00000000
75#define CLK_DIV_DIV_2 0x00000001
76#define CLK_DIV_DIV_3 0x00000002
77#define CLK_DIV_DIV_4 0x00000003
78#define CLK_DIV(i) ((i) << 0)
79
80#define MN_MODE_DUAL_EDGE 0x2
81#define BIT_POS_31 31
82#define BIT_POS_16 16
83#define BIT_POS_6 6
84#define BIT_POS_0 0
85#define BIT_POS_15 15
86
87#define BM(m, l) (((((unsigned int)-1) << (31-m)) >> (31-m+l)) << l)
88#define BVAL(m, l, val) (((val) << l) & BM(m, l))
89
90/* MD Registers */
91#define MD4(m_lsb, m, n_lsb, n) \
92 (BVAL((m_lsb+3), m_lsb, m) | BVAL((n_lsb+3), n_lsb, ~(n)))
93
94#define MD8(m_lsb, m, n_lsb, n) \
95 (BVAL((m_lsb+7), m_lsb, m) | BVAL((n_lsb+7), n_lsb, ~(n)))
96
97/* NS Registers */
98#define NS(n_msb, n_lsb, n, m, mde_lsb, d_msb, d_lsb, d, s_msb, s_lsb, s) \
99 (BVAL(n_msb, n_lsb, ~(n-m)) \
100 | (BVAL((mde_lsb+1), mde_lsb, MN_MODE_DUAL_EDGE) * !!(n)) \
101 | BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
102
103#define NS_MM(n_msb, n_lsb, n, m, d_msb, d_lsb, d, s_msb, s_lsb, s) \
104 (BVAL(n_msb, n_lsb, ~(n-m)) | BVAL(d_msb, d_lsb, (d-1)) \
105 | BVAL(s_msb, s_lsb, s))
106
107#define NS_DIVSRC(d_msb , d_lsb, d, s_msb, s_lsb, s) \
108 (BVAL(d_msb, d_lsb, (d-1)) | BVAL(s_msb, s_lsb, s))
109
110#define NS_DIV(d_msb , d_lsb, d) \
111 BVAL(d_msb, d_lsb, (d-1))
112
113#define NS_SRC_SEL(s_msb, s_lsb, s) \
114 BVAL(s_msb, s_lsb, s)
115
116#define GMAC_AHB_RESET 0x903E24
117
118#define SRC_SEL_PLL0 (0x2 << 0)
119#define MNCNTR_MODE_DUAL_EDGE (0x2 << 5)
120#define MNCNTR_ENABLE (0x1 << 8)
121#define MNCNTR_RST_ACTIVE (0x1 << 7)
122#define N_VAL 15
123
124#define GMAC_CORE_RESET(n) \
125 ((void *)(0x903CBC + ((n) * 0x20)))
126
127#define GMACSEC_CORE_RESET(n) \
128 ((void *)(0x903E28 + ((n - 1) * 4)))
129
130#define GMAC_COREn_CLCK_SRC_CTL(N) \
131 (0x00900000 + (0x3CA0 + (32*(N-1))))
132
133#define GMAC_COREn_CLCK_SRC0_MD(N) \
134 (0x00900000 + (0x3CA4 + (32*(N-1))))
135
136#define GMAC_COREn_CLCK_SRC1_MD(N) \
137 (0x00900000 + (0x3CA8 + (32*(N-1))))
138
139#define GMAC_COREn_CLCK_SRC0_NS(N) \
140 (0x00900000 + (0x3CAC + (32*(N-1))))
141
142#define GMAC_COREn_CLCK_SRC1_NS(N) \
143 (0x00900000 + (0x3CB0 + (32*(N-1))))
144
145#define DISABLE_DUAL_MN8_SEL (0)
146#define DISABLE_CLK_LOW_PWR (0 << 2)
147#define GMAC_CORE_CLCK_ROOT_ENABLE (1 << 1)
148
149/* GMAC_COREn_CLK_SRC[0,1]_MD register bits (Assuming 133MHz) */
150#define GMAC_CORE_CLCK_M 0x32
151#define GMAC_CORE_CLCK_D 0 /* NOT(2*D) value */
152#define GMAC_CORE_CLCK_M_SHIFT 16
153#define GMAC_CORE_CLCK_D_SHIFT 0
154#define GMAC_CORE_CLCK_M_VAL (GMAC_CORE_CLCK_M << GMAC_CORE_CLCK_M_SHIFT)
155#define GMAC_CORE_CLCK_D_VAL (GMAC_CORE_CLCK_D << GMAC_CORE_CLCK_D_SHIFT)
156
157/* GMAC_COREn_CLK_SRC[0,1]_NS register bits (Assuming 133MHz) */
158#define GMAC_CORE_CLCK_N 0x4 /* NOT(N-M) value, N=301 */
159#define GMAC_CORE_CLCK_N_SHIFT 16
160#define GMAC_CORE_CLCK_N_VAL (GMAC_CORE_CLCK_N << GMAC_CORE_CLCK_N_SHIFT)
161#define GMAC_CORE_CLCK_MNCNTR_EN 0x00000100 /* Enable M/N counter */
162#define GMAC_CORE_CLCK_MNCNTR_RST 0x00000080 /* Activate reset for M/N counter */
163#define GMAC_CORE_CLCK_MNCNTR_MODE_MASK 0x00000060 /* M/N counter mode mask */
164#define GMAC_CORE_CLCK_MNCNTR_MODE_SHIFT 5
165#define GMAC_CORE_CLCK_MNCNTR_MODE_DUAL (2 << GMAC_CORE_CLCK_MNCNTR_MODE_SHIFT) /* M/N counter mode dual-edge */
166#define GMAC_CORE_CLCK_PRE_DIV_SEL_MASK 0x00000018 /* Pre divider select mask */
167#define GMAC_CORE_CLCK_PRE_DIV_SEL_SHIFT 3
168#define GMAC_CORE_CLCK_PRE_DIV_SEL_BYP (0 << GMAC_CORE_CLCK_PRE_DIV_SEL_SHIFT) /* Pre divider bypass */
169#define GMAC_CORE_CLCK_SRC_SEL_MASK 0x00000007 /* clk source Mux select mask */
170#define GMAC_CORE_CLCK_SRC_SEL_SHIFT 0
171#define GMAC_CORE_CLCK_SRC_SEL_PLL0 (2 << GMAC_CORE_CLCK_SRC_SEL_SHIFT) /* output of clk source Mux is PLL0 */
172#define GMAC_COREn_CLCK_CTL(N) (0x00900000 + (0x3CB4 + (32*(N-1))))
173
174#define GMAC_COREn_CLCK_INV_DISABLE (0 << 5)
175#define GMAC_COREn_CLCK_BRANCH_ENA (1 << 4)
176
177
178/* Uart specific clock settings */
179
180void uart_pll_vote_clk_enable(unsigned int);
181void uart_clock_config(unsigned int gsbi_port, unsigned int m, unsigned int n,
182 unsigned int d, unsigned int clk_dummy);
183void nand_clock_config(void);
184
185#endif /* __PLATFORM_IPQ860X_CLOCK_H_ */