Arthur Heymans | 7f44929 | 2020-10-22 14:03:46 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Arthur Heymans | 1410224 | 2020-10-22 14:13:14 +0200 | [diff] [blame] | 3 | #include <arch/romstage.h> |
| 4 | #include <cbmem.h> |
| 5 | #include <console/console.h> |
Arthur Heymans | 7f44929 | 2020-10-22 14:03:46 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
| 7 | #include <cpu/x86/smm.h> |
Arthur Heymans | c660600 | 2020-10-19 16:36:30 +0200 | [diff] [blame] | 8 | #include <soc/soc_util.h> |
Arthur Heymans | 7f44929 | 2020-10-22 14:03:46 +0200 | [diff] [blame] | 9 | #include <soc/pci_devs.h> |
Arthur Heymans | c660600 | 2020-10-19 16:36:30 +0200 | [diff] [blame] | 10 | #include <soc/util.h> |
| 11 | #include <security/intel/txt/txt_platform.h> |
Arthur Heymans | 7f44929 | 2020-10-22 14:03:46 +0200 | [diff] [blame] | 12 | |
| 13 | void smm_region(uintptr_t *start, size_t *size) |
| 14 | { |
| 15 | uintptr_t tseg_base = pci_read_config32(VTD_DEV(0), VTD_TSEG_BASE_CSR); |
| 16 | uintptr_t tseg_limit = pci_read_config32(VTD_DEV(0), VTD_TSEG_LIMIT_CSR); |
| 17 | |
| 18 | tseg_base = ALIGN_DOWN(tseg_base, 1 * MiB); |
| 19 | tseg_limit = ALIGN_DOWN(tseg_limit, 1 * MiB); |
| 20 | /* Only the upper [31:20] bits of an address are checked against |
| 21 | * VTD_TSEG_LIMIT_CSR[31:20] which must be below or equal, so this |
| 22 | * effectively means +1MiB for the limit. |
| 23 | */ |
| 24 | tseg_limit += 1 * MiB; |
| 25 | |
| 26 | *start = tseg_base; |
| 27 | *size = tseg_limit - tseg_base; |
| 28 | } |
Arthur Heymans | 1410224 | 2020-10-22 14:13:14 +0200 | [diff] [blame] | 29 | |
| 30 | void fill_postcar_frame(struct postcar_frame *pcf) |
| 31 | { |
Arthur Heymans | 129ed0a | 2020-12-08 13:21:49 +0100 | [diff] [blame] | 32 | const uintptr_t top_of_ram = (uintptr_t)cbmem_top(); |
| 33 | uintptr_t cbmem_base; |
| 34 | size_t cbmem_size; |
Arthur Heymans | 1410224 | 2020-10-22 14:13:14 +0200 | [diff] [blame] | 35 | |
Arthur Heymans | 129ed0a | 2020-12-08 13:21:49 +0100 | [diff] [blame] | 36 | /* Try account for the CBMEM region currently used and for future use */ |
| 37 | cbmem_get_region((void **)&cbmem_base, &cbmem_size); |
Arthur Heymans | 1410224 | 2020-10-22 14:13:14 +0200 | [diff] [blame] | 38 | printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); |
Paul Menzel | a1aca1e | 2021-11-09 08:24:26 +0100 | [diff] [blame] | 39 | printk(BIOS_DEBUG, "cbmem base_ptr: 0x%lx, size: 0x%zx\n", cbmem_base, cbmem_size); |
Arthur Heymans | 129ed0a | 2020-12-08 13:21:49 +0100 | [diff] [blame] | 40 | /* Assume 4MiB will be enough for future cbmem objects (FSP-S, ramstage, ...) */ |
| 41 | cbmem_base -= 4 * MiB; |
| 42 | cbmem_base = ALIGN_DOWN(cbmem_base, 4 * MiB); |
| 43 | |
| 44 | /* Align the top to make sure we don't use too many MTRR's */ |
| 45 | cbmem_size = ALIGN_UP(top_of_ram - cbmem_base, 4 * MiB); |
| 46 | |
| 47 | postcar_frame_add_mtrr(pcf, cbmem_base, cbmem_size, MTRR_TYPE_WRBACK); |
Arthur Heymans | 1410224 | 2020-10-22 14:13:14 +0200 | [diff] [blame] | 48 | /* Cache the TSEG region */ |
| 49 | if (CONFIG(TSEG_STAGE_CACHE)) |
| 50 | postcar_enable_tseg_cache(pcf); |
| 51 | } |
Arthur Heymans | c660600 | 2020-10-19 16:36:30 +0200 | [diff] [blame] | 52 | |
| 53 | #if !defined(__SIMPLE_DEVICE__) |
| 54 | union dpr_register txt_get_chipset_dpr(void) |
| 55 | { |
| 56 | const IIO_UDS *hob = get_iio_uds(); |
| 57 | union dpr_register dpr; |
| 58 | struct device *dev = VTD_DEV(0); |
| 59 | |
| 60 | dpr.raw = 0; |
| 61 | |
Elyes Haouas | f1ba7d6 | 2022-09-13 10:03:44 +0200 | [diff] [blame] | 62 | if (!dev) { |
Arthur Heymans | c660600 | 2020-10-19 16:36:30 +0200 | [diff] [blame] | 63 | printk(BIOS_ERR, "BUS 0: Unable to find VTD PCI dev"); |
| 64 | return dpr; |
| 65 | } |
| 66 | |
| 67 | dpr.raw = pci_read_config32(dev, VTD_LTDPR); |
| 68 | |
| 69 | /* Compare the LTDPR register on all iio stacks */ |
Patrick Rudolph | ac02857 | 2023-07-14 17:44:33 +0200 | [diff] [blame] | 70 | for (int socket = 0, iio = 0; iio < hob->PlatformData.numofIIO; ++socket) { |
| 71 | if (!soc_cpu_is_enabled(socket)) |
| 72 | continue; |
| 73 | iio++; |
Arthur Heymans | c660600 | 2020-10-19 16:36:30 +0200 | [diff] [blame] | 74 | for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { |
| 75 | const STACK_RES *ri = |
| 76 | &hob->PlatformData.IIO_resource[socket].StackRes[stack]; |
Arthur Heymans | 470f1d3 | 2023-08-31 18:19:09 +0200 | [diff] [blame^] | 77 | if (ri->VtdBarAddress == 0) |
Arthur Heymans | c660600 | 2020-10-19 16:36:30 +0200 | [diff] [blame] | 78 | continue; |
| 79 | uint8_t bus = ri->BusBase; |
| 80 | dev = VTD_DEV(bus); |
| 81 | |
Elyes Haouas | f1ba7d6 | 2022-09-13 10:03:44 +0200 | [diff] [blame] | 82 | if (!dev) { |
Arthur Heymans | c660600 | 2020-10-19 16:36:30 +0200 | [diff] [blame] | 83 | printk(BIOS_ERR, "BUS %x: Unable to find VTD PCI dev\n", bus); |
| 84 | dpr.raw = 0; |
| 85 | return dpr; |
| 86 | } |
| 87 | |
| 88 | union dpr_register test_dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) }; |
| 89 | if (dpr.raw != test_dpr.raw) { |
| 90 | printk(BIOS_ERR, "LTDPR not the same on all IIO's"); |
| 91 | dpr.raw = 0; |
| 92 | return dpr; |
| 93 | } |
| 94 | } |
| 95 | } |
| 96 | return dpr; |
| 97 | } |
| 98 | #endif |