Stefan Reinauer | 9d5e36e | 2015-04-27 13:40:16 -0700 | [diff] [blame] | 1 | # TODO These two options look too similar |
Kyösti Mälkki | 5c3f384 | 2014-05-08 15:27:15 +0300 | [diff] [blame] | 2 | config PARALLEL_CPU_INIT |
Sven Schnelle | a2701c6 | 2012-07-29 17:42:52 +0200 | [diff] [blame] | 3 | bool |
Kyösti Mälkki | 5c3f384 | 2014-05-08 15:27:15 +0300 | [diff] [blame] | 4 | default n |
Sven Schnelle | a2701c6 | 2012-07-29 17:42:52 +0200 | [diff] [blame] | 5 | |
Stefan Reinauer | 9d5e36e | 2015-04-27 13:40:16 -0700 | [diff] [blame] | 6 | config PARALLEL_MP |
| 7 | def_bool n |
| 8 | help |
| 9 | This option uses common MP infrastructure for bringing up APs |
| 10 | in parallel. It additionally provides a more flexible mechanism |
| 11 | for sequencing the steps of bringing up the APs. |
| 12 | |
Aaron Durbin | b21e362 | 2016-12-07 00:32:19 -0600 | [diff] [blame] | 13 | config PARALLEL_MP_AP_WORK |
| 14 | def_bool n |
| 15 | depends on PARALLEL_MP |
| 16 | help |
| 17 | Allow APs to do other work after initialization instead of going |
| 18 | to sleep. |
Stefan Reinauer | 9d5e36e | 2015-04-27 13:40:16 -0700 | [diff] [blame] | 19 | |
Patrick Georgi | 0e9a925 | 2009-10-06 20:48:07 +0000 | [diff] [blame] | 20 | config UDELAY_IO |
| 21 | bool |
Aaron Durbin | f70c1bf | 2018-01-24 17:20:11 -0700 | [diff] [blame] | 22 | default y if !UDELAY_LAPIC && !UDELAY_TSC && !UDELAY_TIMER2 && !GENERIC_UDELAY |
Patrick Georgi | 0e9a925 | 2009-10-06 20:48:07 +0000 | [diff] [blame] | 23 | default n |
| 24 | |
| 25 | config UDELAY_LAPIC |
| 26 | bool |
| 27 | default n |
| 28 | |
Aaron Durbin | fd8291c | 2013-04-29 17:18:49 -0500 | [diff] [blame] | 29 | config LAPIC_MONOTONIC_TIMER |
| 30 | def_bool n |
| 31 | depends on UDELAY_LAPIC |
| 32 | select HAVE_MONOTONIC_TIMER |
| 33 | help |
Elyes HAOUAS | d6e9686 | 2016-08-21 10:12:15 +0200 | [diff] [blame] | 34 | Expose monotonic time using the local APIC. |
Aaron Durbin | fd8291c | 2013-04-29 17:18:49 -0500 | [diff] [blame] | 35 | |
Patrick Georgi | e135ac5 | 2012-11-20 11:53:47 +0100 | [diff] [blame] | 36 | config UDELAY_LAPIC_FIXED_FSB |
| 37 | int |
| 38 | |
Ronald G. Minnich | 669c4a9 | 2009-08-29 03:00:51 +0000 | [diff] [blame] | 39 | config UDELAY_TSC |
| 40 | bool |
| 41 | default n |
| 42 | |
Aaron Durbin | 8e73b5d | 2013-05-01 15:27:09 -0500 | [diff] [blame] | 43 | config TSC_CONSTANT_RATE |
| 44 | def_bool n |
| 45 | depends on UDELAY_TSC |
| 46 | help |
| 47 | This option asserts that the TSC ticks at a known constant rate. |
| 48 | Therefore, no TSC calibration is required. |
| 49 | |
Aaron Durbin | e850164 | 2013-04-29 22:22:55 -0500 | [diff] [blame] | 50 | config TSC_MONOTONIC_TIMER |
| 51 | def_bool n |
| 52 | depends on UDELAY_TSC |
| 53 | select HAVE_MONOTONIC_TIMER |
| 54 | help |
| 55 | Expose monotonic time using the TSC. |
| 56 | |
Stefan Reinauer | 9d5e36e | 2015-04-27 13:40:16 -0700 | [diff] [blame] | 57 | # This option is used in code but never selected. |
Stefan Reinauer | 9d5e36e | 2015-04-27 13:40:16 -0700 | [diff] [blame] | 58 | config UDELAY_TIMER2 |
Ronald G. Minnich | 669c4a9 | 2009-08-29 03:00:51 +0000 | [diff] [blame] | 59 | bool |
| 60 | default n |
| 61 | |
Stefan Reinauer | 0db6820 | 2012-08-07 14:44:51 -0700 | [diff] [blame] | 62 | config TSC_SYNC_LFENCE |
| 63 | bool |
| 64 | default n |
| 65 | help |
| 66 | The CPU driver should select this if the CPU needs |
| 67 | to execute an lfence instruction in order to synchronize |
| 68 | rdtsc. This is true for all modern AMD CPUs. |
| 69 | |
| 70 | config TSC_SYNC_MFENCE |
| 71 | bool |
| 72 | default n |
| 73 | help |
| 74 | The CPU driver should select this if the CPU needs |
| 75 | to execute an mfence instruction in order to synchronize |
| 76 | rdtsc. This is true for all modern Intel CPUs. |
| 77 | |
Aaron Durbin | ef10529 | 2016-05-05 10:34:22 -0500 | [diff] [blame] | 78 | config NO_FIXED_XIP_ROM_SIZE |
| 79 | bool |
| 80 | default n |
| 81 | help |
| 82 | The XIP_ROM_SIZE Kconfig variable is used globally on x86 |
| 83 | with the assumption that all chipsets utilize this value. |
| 84 | For the chipsets which do not use the variable it can lead |
| 85 | to unnecessary alignment constraints in cbfs for romstage. |
| 86 | Therefore, allow those chipsets a path to not be burdened. |
| 87 | |
Uwe Hermann | f9d4c2b | 2009-08-25 12:19:28 +0000 | [diff] [blame] | 88 | config XIP_ROM_SIZE |
Patrick Georgi | 0588d19 | 2009-08-12 15:00:51 +0000 | [diff] [blame] | 89 | hex |
Aaron Durbin | ef10529 | 2016-05-05 10:34:22 -0500 | [diff] [blame] | 90 | depends on !NO_FIXED_XIP_ROM_SIZE |
Patrick Georgi | f1ce6f2 | 2010-04-12 09:50:53 +0000 | [diff] [blame] | 91 | default 0x10000 |
Stefan Reinauer | 8aedcbc | 2010-12-16 23:37:17 +0000 | [diff] [blame] | 92 | |
| 93 | config CPU_ADDR_BITS |
| 94 | int |
| 95 | default 36 |
| 96 | |
| 97 | config LOGICAL_CPUS |
| 98 | bool |
| 99 | default y |
| 100 | |
Duncan Laurie | 8bb7723 | 2012-01-09 22:11:25 -0800 | [diff] [blame] | 101 | config SMM_TSEG |
| 102 | bool |
| 103 | default n |
Aaron Durbin | 50a3464 | 2013-01-03 17:38:47 -0600 | [diff] [blame] | 104 | |
| 105 | config SMM_MODULE_HEAP_SIZE |
| 106 | hex |
| 107 | default 0x4000 |
Vladimir Serbinenko | 44cbe10 | 2015-05-28 21:09:31 +0200 | [diff] [blame] | 108 | depends on SMM_TSEG |
Aaron Durbin | 50a3464 | 2013-01-03 17:38:47 -0600 | [diff] [blame] | 109 | help |
| 110 | This option determines the size of the heap within the SMM handler |
| 111 | modules. |
Aaron Durbin | 57686f8 | 2013-03-20 15:50:59 -0500 | [diff] [blame] | 112 | |
Raul E Rangel | d3b8393 | 2018-06-12 10:43:09 -0600 | [diff] [blame] | 113 | config SMM_MODULE_STACK_SIZE |
| 114 | hex |
| 115 | default 0x400 |
| 116 | depends on SMM_TSEG |
| 117 | help |
| 118 | This option determines the size of the stack within the SMM handler |
| 119 | modules. |
| 120 | |
Patrick Georgi | ce2564a | 2015-09-05 20:21:24 +0200 | [diff] [blame] | 121 | config SMM_LAPIC_REMAP_MITIGATION |
| 122 | bool |
| 123 | default y if NORTHBRIDGE_INTEL_I945 |
| 124 | default y if NORTHBRIDGE_INTEL_GM45 |
| 125 | default y if NORTHBRIDGE_INTEL_NEHALEM |
| 126 | default n |
| 127 | |
Damien Zammit | 149c4c5 | 2015-11-28 21:27:05 +1100 | [diff] [blame] | 128 | config SERIALIZED_SMM_INITIALIZATION |
| 129 | bool |
| 130 | default n |
| 131 | help |
| 132 | On some CPUs, there is a race condition in SMM. |
| 133 | This can occur when both hyperthreads change SMM state |
| 134 | variables in parallel without coordination. |
| 135 | Setting this option serializes the SMM initialization |
| 136 | to avoid an ugly hang in the boot process at the cost |
| 137 | of a slightly longer boot time. |
| 138 | |
Aaron Durbin | 57686f8 | 2013-03-20 15:50:59 -0500 | [diff] [blame] | 139 | config X86_AMD_FIXED_MTRRS |
| 140 | bool |
| 141 | default n |
| 142 | help |
| 143 | This option informs the MTRR code to use the RdMem and WrMem fields |
| 144 | in the fixed MTRR MSRs. |
Aaron Durbin | e0785c0 | 2013-10-21 12:15:29 -0500 | [diff] [blame] | 145 | |
Marc Jones | 7868797 | 2015-04-22 23:16:31 -0600 | [diff] [blame] | 146 | config PLATFORM_USES_FSP1_0 |
Martin Roth | a642716 | 2014-04-25 14:12:13 -0600 | [diff] [blame] | 147 | bool |
| 148 | default n |
| 149 | help |
| 150 | Selected for Intel processors/platform combinations that use the |
Marc Jones | 7868797 | 2015-04-22 23:16:31 -0600 | [diff] [blame] | 151 | Intel Firmware Support Package (FSP) 1.0 for initialization. |
Martin Roth | a642716 | 2014-04-25 14:12:13 -0600 | [diff] [blame] | 152 | |
Aaron Durbin | c34713d | 2014-02-25 20:36:56 -0600 | [diff] [blame] | 153 | config MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING |
| 154 | def_bool n |
| 155 | help |
| 156 | On certain platforms a boot speed gain can be realized if mirroring |
| 157 | the payload data stored in non-volatile storage. On x86 systems the |
| 158 | payload would typically live in a memory-mapped SPI part. Copying |
Daniele Forsi | 53847a2 | 2014-07-22 18:00:56 +0200 | [diff] [blame] | 159 | the SPI contents to RAM before performing the load can speed up |
Aaron Durbin | c34713d | 2014-02-25 20:36:56 -0600 | [diff] [blame] | 160 | the boot process. |
David Hendricks | be6f8cb | 2014-03-21 17:09:29 -0700 | [diff] [blame] | 161 | |
Lee Leahy | ae738ac | 2016-07-24 08:03:37 -0700 | [diff] [blame] | 162 | config SOC_SETS_MSRS |
| 163 | bool |
| 164 | default n |
| 165 | help |
| 166 | The SoC requires different access methods for reading and writing |
| 167 | the MSRs. Use SoC specific routines to handle the MSR access. |