Angel Pons | c74dae9 | 2020-04-02 23:48:16 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
| 5 | #include <device/pci.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 7 | #include <device/cardbus.h> |
| 8 | |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 9 | /* |
| 10 | * I don't think this code is quite correct but it is close. |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 11 | * Anyone with a cardbus bridge and a little time should be able |
| 12 | * to make it usable quickly. -- Eric Biederman 24 March 2005 |
| 13 | */ |
| 14 | |
| 15 | /* |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 16 | * IO should be max 256 bytes. However, since we may have a P2P bridge below |
| 17 | * a cardbus bridge, we need 4K. |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 18 | */ |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 19 | #define CARDBUS_IO_SIZE 4096 |
| 20 | #define CARDBUS_MEM_SIZE (32 * 1024 * 1024) |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 21 | |
Elyes HAOUAS | e18cbea | 2018-05-02 21:20:59 +0200 | [diff] [blame] | 22 | static void cardbus_record_bridge_resource(struct device *dev, resource_t moving, |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 23 | resource_t min_size, unsigned int index, unsigned long type) |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 24 | { |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 25 | struct resource *resource; |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 26 | unsigned long gran; |
| 27 | resource_t step; |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 28 | |
| 29 | /* Initialize the constraints on the current bus. */ |
Myles Watson | 03adcfd | 2010-06-07 16:51:11 +0000 | [diff] [blame] | 30 | resource = NULL; |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 31 | if (!moving) |
| 32 | return; |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 33 | |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 34 | resource = new_resource(dev, index); |
| 35 | resource->size = 0; |
| 36 | gran = 0; |
| 37 | step = 1; |
| 38 | while ((moving & step) == 0) { |
| 39 | gran += 1; |
| 40 | step <<= 1; |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 41 | } |
Uwe Hermann | e487047 | 2010-11-04 23:23:47 +0000 | [diff] [blame] | 42 | resource->gran = gran; |
| 43 | resource->align = gran; |
| 44 | resource->limit = moving | (step - 1); |
| 45 | resource->flags = type; |
| 46 | |
| 47 | /* Don't let the minimum size exceed what we can put in the resource. */ |
| 48 | if ((min_size - 1) > resource->limit) |
| 49 | min_size = resource->limit + 1; |
| 50 | |
| 51 | resource->size = min_size; |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 52 | } |
| 53 | |
Elyes HAOUAS | e18cbea | 2018-05-02 21:20:59 +0200 | [diff] [blame] | 54 | void cardbus_read_resources(struct device *dev) |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 55 | { |
| 56 | resource_t moving_base, moving_limit, moving; |
| 57 | unsigned long type; |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 58 | u16 ctl; |
Ronald G. Minnich | 43225bc | 2005-11-22 00:07:02 +0000 | [diff] [blame] | 59 | |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 60 | /* See if needs a card control registers base address. */ |
Ronald G. Minnich | 43225bc | 2005-11-22 00:07:02 +0000 | [diff] [blame] | 61 | |
| 62 | pci_get_resource(dev, PCI_BASE_ADDRESS_0); |
| 63 | |
| 64 | compact_resources(dev); |
| 65 | |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 66 | /* See which bridge I/O resources are implemented. */ |
| 67 | moving_base = pci_moving_config32(dev, PCI_CB_IO_BASE_0); |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 68 | moving_limit = pci_moving_config32(dev, PCI_CB_IO_LIMIT_0); |
| 69 | moving = moving_base & moving_limit; |
| 70 | |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 71 | /* Initialize the I/O space constraints on the current bus. */ |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 72 | cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE, |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 73 | PCI_CB_IO_BASE_0, IORESOURCE_IO); |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 74 | |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 75 | /* See which bridge I/O resources are implemented. */ |
| 76 | moving_base = pci_moving_config32(dev, PCI_CB_IO_BASE_1); |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 77 | moving_limit = pci_moving_config32(dev, PCI_CB_IO_LIMIT_1); |
| 78 | moving = moving_base & moving_limit; |
| 79 | |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 80 | /* Initialize the I/O space constraints on the current bus. */ |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 81 | cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE, |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 82 | PCI_CB_IO_BASE_1, IORESOURCE_IO); |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 83 | |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 84 | /* If I can, enable prefetch for mem0. */ |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 85 | ctl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL); |
| 86 | ctl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; |
| 87 | ctl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; |
| 88 | ctl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; |
| 89 | pci_write_config16(dev, PCI_CB_BRIDGE_CONTROL, ctl); |
| 90 | ctl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL); |
| 91 | |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 92 | /* See which bridge memory resources are implemented. */ |
| 93 | moving_base = pci_moving_config32(dev, PCI_CB_MEMORY_BASE_0); |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 94 | moving_limit = pci_moving_config32(dev, PCI_CB_MEMORY_LIMIT_0); |
| 95 | moving = moving_base & moving_limit; |
| 96 | |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 97 | /* Initialize the memory space constraints on the current bus. */ |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 98 | type = IORESOURCE_MEM; |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 99 | if (ctl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 100 | type |= IORESOURCE_PREFETCH; |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 101 | cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE, |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 102 | PCI_CB_MEMORY_BASE_0, type); |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 103 | |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 104 | /* See which bridge memory resources are implemented. */ |
| 105 | moving_base = pci_moving_config32(dev, PCI_CB_MEMORY_BASE_1); |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 106 | moving_limit = pci_moving_config32(dev, PCI_CB_MEMORY_LIMIT_1); |
| 107 | moving = moving_base & moving_limit; |
| 108 | |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 109 | /* Initialize the memory space constraints on the current bus. */ |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 110 | cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE, |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 111 | PCI_CB_MEMORY_BASE_1, IORESOURCE_MEM); |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 112 | |
| 113 | compact_resources(dev); |
| 114 | } |
| 115 | |
Elyes HAOUAS | e18cbea | 2018-05-02 21:20:59 +0200 | [diff] [blame] | 116 | void cardbus_enable_resources(struct device *dev) |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 117 | { |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 118 | u16 ctrl; |
| 119 | |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 120 | ctrl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL); |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 121 | ctrl |= (dev->link_list->bridge_ctrl & ( |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 122 | PCI_BRIDGE_CTL_VGA | |
| 123 | PCI_BRIDGE_CTL_MASTER_ABORT | |
| 124 | PCI_BRIDGE_CTL_BUS_RESET)); |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 125 | /* Error check */ |
Kyösti Mälkki | 382e216 | 2019-09-21 16:19:32 +0300 | [diff] [blame] | 126 | ctrl |= (PCI_CB_BRIDGE_CTL_PARITY | PCI_CB_BRIDGE_CTL_SERR); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 127 | printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl); |
Kyösti Mälkki | 0bca050 | 2019-09-21 16:21:47 +0300 | [diff] [blame] | 128 | pci_write_config16(dev, PCI_CB_BRIDGE_CONTROL, ctrl); |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 129 | |
| 130 | pci_dev_enable_resources(dev); |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 131 | } |
| 132 | |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 133 | struct device_operations default_cardbus_ops_bus = { |
| 134 | .read_resources = cardbus_read_resources, |
| 135 | .set_resources = pci_dev_set_resources, |
| 136 | .enable_resources = cardbus_enable_resources, |
Uwe Hermann | d453dd0 | 2010-10-18 00:00:57 +0000 | [diff] [blame] | 137 | .scan_bus = pci_scan_bridge, |
Yinghai Lu | 304f24c | 2005-07-08 02:56:47 +0000 | [diff] [blame] | 138 | .reset_bus = pci_bus_reset, |
| 139 | }; |