Felix Held | 4a8cd72 | 2020-04-18 22:26:39 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | # This file is part of the coreboot project. |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 3 | |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 4 | config SOC_AMD_PICASSO |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 5 | bool |
| 6 | help |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 7 | AMD Picasso support |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 8 | |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 9 | if SOC_AMD_PICASSO |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 10 | |
| 11 | config CPU_SPECIFIC_OPTIONS |
| 12 | def_bool y |
| 13 | select ARCH_BOOTBLOCK_X86_32 |
| 14 | select ARCH_VERSTAGE_X86_32 |
| 15 | select ARCH_ROMSTAGE_X86_32 |
| 16 | select ARCH_RAMSTAGE_X86_32 |
| 17 | select X86_AMD_FIXED_MTRRS |
Marshall Dawson | 34c3056 | 2019-07-16 15:18:00 -0600 | [diff] [blame] | 18 | select X86_AMD_INIT_SIPI |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 19 | select ACPI_AMD_HARDWARE_SLEEP_VALUES |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 20 | select DRIVERS_I2C_DESIGNWARE |
| 21 | select GENERIC_GPIO_LIB |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 22 | select IOAPIC |
| 23 | select HAVE_USBDEBUG_OPTIONS |
Marshall Dawson | 80d0b01 | 2019-06-19 12:29:23 -0600 | [diff] [blame] | 24 | select TSC_MONOTONIC_TIMER |
Richard Spiegel | 65562cd65 | 2019-08-21 10:27:05 -0700 | [diff] [blame] | 25 | select SOC_AMD_COMMON_BLOCK_SPI |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 26 | select TSC_SYNC_LFENCE |
Marshall Dawson | 80d0b01 | 2019-06-19 12:29:23 -0600 | [diff] [blame] | 27 | select UDELAY_TSC |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 28 | select SOC_AMD_COMMON |
| 29 | select SOC_AMD_COMMON_BLOCK |
| 30 | select SOC_AMD_COMMON_BLOCK_IOMMU |
| 31 | select SOC_AMD_COMMON_BLOCK_ACPIMMIO |
| 32 | select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS |
| 33 | select SOC_AMD_COMMON_BLOCK_ACPI |
Furquan Shaikh | 9e1a49c | 2020-04-23 14:01:12 -0700 | [diff] [blame] | 34 | select SOC_AMD_COMMON_BLOCK_GRAPHICS |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 35 | select SOC_AMD_COMMON_BLOCK_LPC |
| 36 | select SOC_AMD_COMMON_BLOCK_PCI |
| 37 | select SOC_AMD_COMMON_BLOCK_HDA |
| 38 | select SOC_AMD_COMMON_BLOCK_SATA |
Aaron Durbin | 3d2e18a | 2020-01-28 11:20:05 -0700 | [diff] [blame] | 39 | select SOC_AMD_COMMON_BLOCK_SMBUS |
Marshall Dawson | 5a73fc3 | 2020-01-24 09:42:57 -0700 | [diff] [blame] | 40 | select SOC_AMD_COMMON_BLOCK_PSP_GEN2 |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 41 | select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH |
| 42 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 43 | select PARALLEL_MP |
| 44 | select PARALLEL_MP_AP_WORK |
| 45 | select HAVE_SMI_HANDLER |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 46 | select SSE2 |
| 47 | select RTC |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 48 | |
Kyösti Mälkki | 9c55ee3 | 2019-07-22 09:34:50 +0300 | [diff] [blame] | 49 | config HAVE_BOOTBLOCK |
| 50 | bool |
| 51 | default n |
| 52 | |
Felix Held | 8cb5c30 | 2020-03-27 20:04:32 +0100 | [diff] [blame] | 53 | config AMD_FP5 |
| 54 | def_bool y if !AMD_FT5 |
| 55 | help |
| 56 | The FP5 package supports higher-wattage parts and dual channel DDR4 memory. |
| 57 | |
| 58 | config AMD_FT5 |
| 59 | def_bool n |
| 60 | help |
| 61 | The FT5 package supports low-power parts and single-channel DDR4 memory. |
| 62 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 63 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 64 | hex |
| 65 | default 0x1600 |
| 66 | help |
| 67 | Increase this value if preram cbmem console is getting truncated |
| 68 | |
| 69 | config CPU_ADDR_BITS |
| 70 | int |
| 71 | default 48 |
| 72 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 73 | config MMCONF_BASE_ADDRESS |
| 74 | hex |
| 75 | default 0xF8000000 |
| 76 | |
| 77 | config MMCONF_BUS_NUMBER |
| 78 | int |
| 79 | default 64 |
| 80 | |
| 81 | config VGA_BIOS_ID |
| 82 | string |
Marshall Dawson | 0d441da | 2019-07-09 18:19:05 -0500 | [diff] [blame] | 83 | default "1002,15d8" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 84 | help |
| 85 | The default VGA BIOS PCI vendor/device ID should be set to the |
| 86 | result of the map_oprom_vendev() function in northbridge.c. |
| 87 | |
| 88 | config VGA_BIOS_FILE |
| 89 | string |
Marshall Dawson | 0d441da | 2019-07-09 18:19:05 -0500 | [diff] [blame] | 90 | default "3rdparty/blobs/soc/amd/picasso/PicassoGenericVbios.bin" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 91 | |
| 92 | config S3_VGA_ROM_RUN |
| 93 | bool |
| 94 | default n |
| 95 | |
| 96 | config HEAP_SIZE |
| 97 | hex |
| 98 | default 0xc0000 |
| 99 | |
| 100 | config EHCI_BAR |
| 101 | hex |
| 102 | default 0xfef00000 |
| 103 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 104 | config SERIRQ_CONTINUOUS_MODE |
| 105 | bool |
| 106 | default n |
| 107 | help |
| 108 | Set this option to y for serial IRQ in continuous mode. |
| 109 | Otherwise it is in quiet mode. |
| 110 | |
Marshall Dawson | bc4c903 | 2019-06-11 12:18:20 -0600 | [diff] [blame] | 111 | config PICASSO_ACPI_IO_BASE |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 112 | hex |
| 113 | default 0x400 |
| 114 | help |
| 115 | Base address for the ACPI registers. |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 116 | |
Marshall Dawson | bc4c903 | 2019-06-11 12:18:20 -0600 | [diff] [blame] | 117 | config PICASSO_UART |
| 118 | bool "UART controller on Picasso" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 119 | default n |
| 120 | select DRIVERS_UART_8250MEM |
| 121 | select DRIVERS_UART_8250MEM_32 |
| 122 | select NO_UART_ON_SUPERIO |
| 123 | select UART_OVERRIDE_REFCLK |
| 124 | help |
Marshall Dawson | c0b8d0d | 2019-06-20 10:29:29 -0600 | [diff] [blame] | 125 | There are four memory-mapped UARTs controllers in Picasso at: |
| 126 | 0: 0xfedc9000 |
| 127 | 1: 0xfedca000 |
| 128 | 2: 0xfedc3000 |
| 129 | 3: 0xfedcf000 |
| 130 | |
| 131 | choice PICASSO_UART_CLOCK_SOURCE |
| 132 | prompt "UART Frequency" |
| 133 | depends on PICASSO_UART |
| 134 | default PICASSO_UART_48MZ |
| 135 | |
| 136 | config PICASSO_UART_48MZ |
| 137 | bool "48 MHz clock" |
| 138 | help |
| 139 | Select this option for the most compatibility. |
| 140 | |
| 141 | config PICASSO_UART_1_8MZ |
| 142 | bool "1.8432 MHz clock" |
| 143 | help |
| 144 | Select this option if an old payload or Linux ttyS0 arguments |
| 145 | require it. |
| 146 | |
| 147 | endchoice |
| 148 | |
| 149 | config PICASSO_UART_LEGACY |
| 150 | bool "Decode legacy I/O range" |
| 151 | depends on PICASSO_UART |
| 152 | help |
| 153 | Assign I/O 3F8, 2F8, etc. to a Picasso UART. Only a single UART may |
| 154 | decode legacy addresses and this option enables the one used for the |
| 155 | console. A UART accessed with I/O does not allow all the features |
| 156 | of MMIO. The MMIO decode is still present when this option is used. |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 157 | |
| 158 | config CONSOLE_UART_BASE_ADDRESS |
Marshall Dawson | c0b8d0d | 2019-06-20 10:29:29 -0600 | [diff] [blame] | 159 | depends on CONSOLE_SERIAL && PICASSO_UART |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 160 | hex |
Marshall Dawson | c0b8d0d | 2019-06-20 10:29:29 -0600 | [diff] [blame] | 161 | default 0xfedc9000 if UART_FOR_CONSOLE = 0 |
| 162 | default 0xfedca000 if UART_FOR_CONSOLE = 1 |
| 163 | default 0xfedc3000 if UART_FOR_CONSOLE = 2 |
| 164 | default 0xfedcf000 if UART_FOR_CONSOLE = 3 |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 165 | |
| 166 | config SMM_TSEG_SIZE |
| 167 | hex |
| 168 | default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER |
| 169 | default 0x0 |
| 170 | |
| 171 | config SMM_RESERVED_SIZE |
| 172 | hex |
| 173 | default 0x150000 |
| 174 | |
| 175 | config SMM_MODULE_STACK_SIZE |
| 176 | hex |
| 177 | default 0x800 |
| 178 | |
| 179 | config ACPI_CPU_STRING |
| 180 | string |
| 181 | default "\\_PR.P%03d" |
| 182 | |
| 183 | config ACPI_BERT |
| 184 | bool "Build ACPI BERT Table" |
| 185 | default y |
| 186 | depends on HAVE_ACPI_TABLES |
| 187 | help |
| 188 | Report Machine Check errors identified in POST to the OS in an |
| 189 | ACPI Boot Error Record Table. This option reserves an 8MB region |
| 190 | for building the error structures. |
| 191 | |
Marshall Dawson | 901cb9c | 2020-01-21 14:53:45 -0700 | [diff] [blame] | 192 | config ACPI_BERT_SIZE |
| 193 | hex |
| 194 | default 0x4000 |
| 195 | help |
| 196 | Specify the amount of DRAM reserved for gathering the data used to |
| 197 | generate the ACPI table. |
| 198 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 199 | config RO_REGION_ONLY |
| 200 | string |
| 201 | depends on CHROMEOS |
| 202 | default "apu/amdfw" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 203 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 204 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 205 | int |
Martin Roth | 4017de0 | 2019-12-16 23:21:05 -0700 | [diff] [blame] | 206 | default 150 |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 207 | |
Marshall Dawson | 39a4ac1 | 2019-06-20 16:28:33 -0600 | [diff] [blame] | 208 | config PICASSO_LPC_IOMUX |
| 209 | bool |
| 210 | help |
| 211 | Picasso's LPC bus signals are MUXed with some of the EMMC signals. |
| 212 | Select this option if LPC signals are required. |
| 213 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 214 | config MAINBOARD_POWER_RESTORE |
| 215 | def_bool n |
| 216 | help |
| 217 | This option determines what state to go to once power is restored |
| 218 | after having been lost in S0. Select this option to automatically |
| 219 | return to S0. Otherwise the system will remain in S5 once power |
| 220 | is restored. |
| 221 | |
| 222 | menu "PSP Configuration Options" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 223 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 224 | config AMDFW_OUTSIDE_CBFS |
| 225 | bool "The AMD firmware is outside CBFS" |
| 226 | default n |
| 227 | help |
| 228 | The AMDFW (PSP) is typically locatable in cbfs. Select this |
| 229 | option to manually attach the generated amdfw.rom outside of |
| 230 | cbfs. The location is selected by the FWM position. |
| 231 | |
| 232 | config AMD_FWM_POSITION_INDEX |
| 233 | int "Firmware Directory Table location (0 to 5)" |
| 234 | range 0 5 |
| 235 | default 0 if BOARD_ROMSIZE_KB_512 |
| 236 | default 1 if BOARD_ROMSIZE_KB_1024 |
| 237 | default 2 if BOARD_ROMSIZE_KB_2048 |
| 238 | default 3 if BOARD_ROMSIZE_KB_4096 |
| 239 | default 4 if BOARD_ROMSIZE_KB_8192 |
| 240 | default 5 if BOARD_ROMSIZE_KB_16384 |
| 241 | help |
| 242 | Typically this is calculated by the ROM size, but there may |
| 243 | be situations where you want to put the firmware directory |
| 244 | table in a different location. |
| 245 | 0: 512 KB - 0xFFFA0000 |
| 246 | 1: 1 MB - 0xFFF20000 |
| 247 | 2: 2 MB - 0xFFE20000 |
| 248 | 3: 4 MB - 0xFFC20000 |
| 249 | 4: 8 MB - 0xFF820000 |
| 250 | 5: 16 MB - 0xFF020000 |
| 251 | |
| 252 | comment "AMD Firmware Directory Table set to location for 512KB ROM" |
| 253 | depends on AMD_FWM_POSITION_INDEX = 0 |
| 254 | comment "AMD Firmware Directory Table set to location for 1MB ROM" |
| 255 | depends on AMD_FWM_POSITION_INDEX = 1 |
| 256 | comment "AMD Firmware Directory Table set to location for 2MB ROM" |
| 257 | depends on AMD_FWM_POSITION_INDEX = 2 |
| 258 | comment "AMD Firmware Directory Table set to location for 4MB ROM" |
| 259 | depends on AMD_FWM_POSITION_INDEX = 3 |
| 260 | comment "AMD Firmware Directory Table set to location for 8MB ROM" |
| 261 | depends on AMD_FWM_POSITION_INDEX = 4 |
| 262 | comment "AMD Firmware Directory Table set to location for 16MB ROM" |
| 263 | depends on AMD_FWM_POSITION_INDEX = 5 |
| 264 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 265 | config AMD_PUBKEY_FILE |
| 266 | string "AMD public Key" |
| 267 | default "3rdparty/blobs/soc/amd/picasso/PSP/AmdPubKeyRV.bin" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 268 | |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 269 | config PSP_APCB_FILE |
| 270 | string "APCB file" |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 271 | help |
Marshall Dawson | 4357a82 | 2019-09-25 11:07:56 -0600 | [diff] [blame] | 272 | The name of the AGESA Parameter Customization Block. This image is |
| 273 | instance ID 0 in the PSP's BIOS Directory Table. |
| 274 | |
| 275 | config PSP_APCB1_FILE |
| 276 | string |
| 277 | help |
| 278 | If specified, this image is instance ID 1 in the PSP's BIOS |
| 279 | Directory Table. |
| 280 | |
| 281 | config PSP_APCB2_FILE |
| 282 | string |
| 283 | help |
| 284 | If specified, this image is instance ID 2 in the PSP's BIOS |
| 285 | Directory Table. |
| 286 | |
| 287 | config PSP_APCB3_FILE |
| 288 | string |
| 289 | help |
| 290 | If specified, this image is instance ID 3 in the PSP's BIOS |
| 291 | Directory Table. |
| 292 | |
| 293 | config PSP_APCB4_FILE |
| 294 | string |
| 295 | help |
| 296 | If specified, this image is instance ID 4 in the PSP's BIOS |
| 297 | Directory Table. |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 298 | |
| 299 | config PSP_APOB_DESTINATION |
| 300 | hex |
| 301 | default 0x9f00000 |
| 302 | help |
| 303 | Location in DRAM where the PSP will copy the AGESA PSP Output |
| 304 | Block. |
| 305 | |
| 306 | config PSP_APOB_NV_ADDRESS |
| 307 | hex "Base address of APOB NV" |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 308 | help |
| 309 | Location in flash where the PSP can find the S3 restore information. |
| 310 | Place this on a boundary that the flash device can erase. |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 311 | |
| 312 | config PSP_APOB_NV_SIZE |
| 313 | hex "Size of APOB NV to be reserved" |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 314 | help |
| 315 | Size of the S3 restore information. Make this a multiple of the |
| 316 | size the flash device can erase. |
Marshall Dawson | 6261141 | 2019-06-19 11:46:06 -0600 | [diff] [blame] | 317 | |
| 318 | config USE_PSPSCUREOS |
| 319 | bool "Include PSP SecureOS blobs in PSP build" |
| 320 | default y |
| 321 | help |
| 322 | Include the PspSecureOs and PspTrustlet binaries in the PSP build. |
| 323 | |
| 324 | If unsure, answer 'y' |
| 325 | |
| 326 | config PSP_LOAD_MP2_FW |
| 327 | bool "Include MP2 blobs in PSP build" |
| 328 | default y |
| 329 | help |
| 330 | Include the MP2 firmwares and configuration into the PSP build. |
| 331 | |
| 332 | If unsure, answer 'y' |
| 333 | |
| 334 | config PSP_LOAD_S0I3_FW |
| 335 | bool "Include S0I3 blob in PSP build" |
| 336 | help |
| 337 | Select this item to include the S0i3 file into the PSP build. |
| 338 | |
| 339 | config HAVE_PSP_WHITELIST_FILE |
| 340 | bool "Include a debug whitelist file in PSP build" |
| 341 | default n |
| 342 | help |
| 343 | Support secured unlock prior to reset using a whitelisted |
| 344 | number? This feature requires a signed whitelist image and |
| 345 | bootloader from AMD. |
| 346 | |
| 347 | If unsure, answer 'n' |
| 348 | |
| 349 | config PSP_WHITELIST_FILE |
| 350 | string "Debug whitelist file name" |
| 351 | depends on HAVE_PSP_WHITELIST_FILE |
| 352 | default "3rdparty/blobs/soc/amd/picasso/PSP/wtl-rvn.sbin" |
| 353 | |
| 354 | endmenu |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 355 | |
Martin Roth | 1f33762 | 2019-04-22 16:08:31 -0600 | [diff] [blame] | 356 | endif # SOC_AMD_PICASSO |