Angel Pons | a2ee761 | 2020-04-04 18:51:15 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Elyes HAOUAS | 27d02d8 | 2019-05-15 21:11:39 +0200 | [diff] [blame] | 2 | |
| 3 | #include <commonlib/helpers.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 4 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 5 | #include <device/mmio.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 6 | #include <delay.h> |
| 7 | #include <timer.h> |
| 8 | #include <soc/addressmap.h> |
| 9 | #include <soc/clock.h> |
| 10 | #include <device/device.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 11 | #include <soc/nvidia/tegra/types.h> |
| 12 | #include <soc/nvidia/tegra/dc.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 13 | #include <soc/display.h> |
| 14 | #include <soc/mipi_dsi.h> |
| 15 | #include <soc/mipi_display.h> |
| 16 | #include <soc/tegra_dsi.h> |
| 17 | #include <soc/mipi-phy.h> |
Elyes HAOUAS | 27d02d8 | 2019-05-15 21:11:39 +0200 | [diff] [blame] | 18 | #include <types.h> |
| 19 | |
| 20 | #include "chip.h" |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 21 | #include "jdi_25x18_display/panel-jdi-lpm102a188a.h" |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 22 | |
| 23 | struct tegra_mipi_device mipi_device_data[NUM_DSI]; |
| 24 | |
| 25 | struct tegra_dsi dsi_data[NUM_DSI] = { |
| 26 | { |
| 27 | .regs = (void *)TEGRA_DSIA_BASE, |
| 28 | .channel = 0, |
| 29 | .slave = &dsi_data[DSI_B], |
| 30 | .master = NULL, |
| 31 | .video_fifo_depth = MAX_DSI_VIDEO_FIFO_DEPTH, |
| 32 | .host_fifo_depth = MAX_DSI_HOST_FIFO_DEPTH, |
| 33 | }, |
| 34 | { |
| 35 | .regs = (void *)TEGRA_DSIB_BASE, |
| 36 | .channel = 0, |
| 37 | .slave = NULL, |
| 38 | .master = &dsi_data[DSI_A], |
| 39 | .video_fifo_depth = MAX_DSI_VIDEO_FIFO_DEPTH, |
| 40 | .host_fifo_depth = MAX_DSI_HOST_FIFO_DEPTH, |
| 41 | }, |
| 42 | }; |
| 43 | |
| 44 | static const u32 init_reg[] = { |
| 45 | DSI_INT_ENABLE, |
| 46 | DSI_INT_STATUS, |
| 47 | DSI_INT_MASK, |
| 48 | DSI_INIT_SEQ_DATA_0, |
| 49 | DSI_INIT_SEQ_DATA_1, |
| 50 | DSI_INIT_SEQ_DATA_2, |
| 51 | DSI_INIT_SEQ_DATA_3, |
| 52 | DSI_INIT_SEQ_DATA_4, |
| 53 | DSI_INIT_SEQ_DATA_5, |
| 54 | DSI_INIT_SEQ_DATA_6, |
| 55 | DSI_INIT_SEQ_DATA_7, |
| 56 | DSI_INIT_SEQ_DATA_15, |
| 57 | DSI_DCS_CMDS, |
| 58 | DSI_PKT_SEQ_0_LO, |
| 59 | DSI_PKT_SEQ_1_LO, |
| 60 | DSI_PKT_SEQ_2_LO, |
| 61 | DSI_PKT_SEQ_3_LO, |
| 62 | DSI_PKT_SEQ_4_LO, |
| 63 | DSI_PKT_SEQ_5_LO, |
| 64 | DSI_PKT_SEQ_0_HI, |
| 65 | DSI_PKT_SEQ_1_HI, |
| 66 | DSI_PKT_SEQ_2_HI, |
| 67 | DSI_PKT_SEQ_3_HI, |
| 68 | DSI_PKT_SEQ_4_HI, |
| 69 | DSI_PKT_SEQ_5_HI, |
| 70 | DSI_CONTROL, |
| 71 | DSI_HOST_CONTROL, |
| 72 | DSI_PAD_CONTROL_0, |
| 73 | DSI_PAD_CONTROL_CD, |
| 74 | DSI_SOL_DELAY, |
| 75 | DSI_MAX_THRESHOLD, |
| 76 | DSI_TRIGGER, |
| 77 | DSI_TX_CRC, |
| 78 | DSI_INIT_SEQ_CONTROL, |
| 79 | DSI_PKT_LEN_0_1, |
| 80 | DSI_PKT_LEN_2_3, |
| 81 | DSI_PKT_LEN_4_5, |
| 82 | DSI_PKT_LEN_6_7, |
| 83 | }; |
| 84 | |
| 85 | static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host) |
| 86 | { |
| 87 | return container_of(host, struct tegra_dsi, host); |
| 88 | } |
| 89 | |
| 90 | /* |
| 91 | * non-burst mode with sync pulses |
| 92 | */ |
| 93 | static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = { |
| 94 | [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | |
| 95 | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | |
| 96 | PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | |
| 97 | PKT_LP, |
| 98 | [ 1] = 0, |
| 99 | [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) | |
| 100 | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | |
| 101 | PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | |
| 102 | PKT_LP, |
| 103 | [ 3] = 0, |
| 104 | [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | |
| 105 | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | |
| 106 | PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | |
| 107 | PKT_LP, |
| 108 | [ 5] = 0, |
| 109 | [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | |
| 110 | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | |
| 111 | PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0), |
| 112 | [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) | |
| 113 | PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) | |
| 114 | PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4), |
| 115 | [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | |
| 116 | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | |
| 117 | PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | |
| 118 | PKT_LP, |
| 119 | [ 9] = 0, |
| 120 | [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | |
| 121 | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | |
| 122 | PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0), |
| 123 | [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) | |
| 124 | PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) | |
| 125 | PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4), |
| 126 | }; |
| 127 | |
| 128 | /* |
| 129 | * non-burst mode with sync events |
| 130 | */ |
| 131 | static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = { |
| 132 | [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | |
| 133 | PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | |
| 134 | PKT_LP, |
| 135 | [ 1] = 0, |
| 136 | [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | |
| 137 | PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | |
| 138 | PKT_LP, |
| 139 | [ 3] = 0, |
| 140 | [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | |
| 141 | PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | |
| 142 | PKT_LP, |
| 143 | [ 5] = 0, |
| 144 | |
| 145 | [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | |
| 146 | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) | |
| 147 | PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3), |
| 148 | |
| 149 | [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4), |
| 150 | [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | |
| 151 | PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | |
| 152 | PKT_LP, |
| 153 | [ 9] = 0, |
| 154 | |
| 155 | [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | |
| 156 | PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) | |
| 157 | PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3), |
| 158 | |
| 159 | [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4), |
| 160 | }; |
| 161 | |
| 162 | static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = { |
| 163 | [ 0] = 0, |
| 164 | [ 1] = 0, |
| 165 | [ 2] = 0, |
| 166 | [ 3] = 0, |
| 167 | [ 4] = 0, |
| 168 | [ 5] = 0, |
| 169 | [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP, |
| 170 | [ 7] = 0, |
| 171 | [ 8] = 0, |
| 172 | [ 9] = 0, |
| 173 | [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP, |
| 174 | [11] = 0, |
| 175 | }; |
| 176 | |
| 177 | static int tegra_dsi_set_phy_timing(struct tegra_dsi *dsi) |
| 178 | { |
| 179 | int err; |
| 180 | |
| 181 | err = mipi_dphy_set_timing(dsi); |
| 182 | if (err < 0) { |
| 183 | printk(BIOS_ERR, "failed to set D-PHY timing: %d\n", err); |
| 184 | return err; |
| 185 | } |
| 186 | |
| 187 | if (dsi->slave) |
| 188 | tegra_dsi_set_phy_timing(dsi->slave); |
| 189 | return 0; |
| 190 | } |
| 191 | |
| 192 | static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format, |
| 193 | unsigned int *mulp, unsigned int *divp) |
| 194 | { |
| 195 | switch (format) { |
| 196 | case MIPI_DSI_FMT_RGB666_PACKED: |
| 197 | case MIPI_DSI_FMT_RGB888: |
| 198 | *mulp = 3; |
| 199 | *divp = 1; |
| 200 | break; |
| 201 | |
| 202 | case MIPI_DSI_FMT_RGB565: |
| 203 | *mulp = 2; |
| 204 | *divp = 1; |
| 205 | break; |
| 206 | |
| 207 | case MIPI_DSI_FMT_RGB666: |
| 208 | *mulp = 9; |
| 209 | *divp = 4; |
| 210 | break; |
| 211 | |
| 212 | default: |
| 213 | return -EINVAL; |
| 214 | } |
| 215 | return 0; |
| 216 | } |
| 217 | |
| 218 | static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format, |
| 219 | enum tegra_dsi_format *fmt) |
| 220 | { |
| 221 | switch (format) { |
| 222 | case MIPI_DSI_FMT_RGB888: |
| 223 | *fmt = TEGRA_DSI_FORMAT_24P; |
| 224 | break; |
| 225 | |
| 226 | case MIPI_DSI_FMT_RGB666: |
| 227 | *fmt = TEGRA_DSI_FORMAT_18NP; |
| 228 | break; |
| 229 | |
| 230 | case MIPI_DSI_FMT_RGB666_PACKED: |
| 231 | *fmt = TEGRA_DSI_FORMAT_18P; |
| 232 | break; |
| 233 | |
| 234 | case MIPI_DSI_FMT_RGB565: |
| 235 | *fmt = TEGRA_DSI_FORMAT_16P; |
| 236 | break; |
| 237 | |
| 238 | default: |
| 239 | return -EINVAL; |
| 240 | } |
| 241 | return 0; |
| 242 | } |
| 243 | |
| 244 | static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start, |
| 245 | unsigned int size) |
| 246 | { |
| 247 | u32 value; |
| 248 | |
| 249 | tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START); |
| 250 | tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE); |
| 251 | |
| 252 | value = DSI_GANGED_MODE_CONTROL_ENABLE; |
| 253 | tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL); |
| 254 | } |
| 255 | |
| 256 | static void tegra_dsi_enable(struct tegra_dsi *dsi) |
| 257 | { |
| 258 | u32 value; |
| 259 | |
| 260 | value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); |
| 261 | value |= DSI_POWER_CONTROL_ENABLE; |
| 262 | tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); |
| 263 | |
| 264 | if (dsi->slave) |
| 265 | tegra_dsi_enable(dsi->slave); |
| 266 | } |
| 267 | |
| 268 | static int tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe, |
| 269 | const struct soc_nvidia_tegra210_config *mode) |
| 270 | { |
| 271 | unsigned int hact, hsw, hbp, hfp, i, mul, div; |
| 272 | enum tegra_dsi_format format; |
| 273 | const u32 *pkt_seq; |
| 274 | u32 value; |
| 275 | int err; |
| 276 | |
| 277 | if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { |
| 278 | printk(BIOS_SPEW, "Non-burst video mode with sync pulses\n"); |
| 279 | pkt_seq = pkt_seq_video_non_burst_sync_pulses; |
| 280 | } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) { |
| 281 | printk(BIOS_SPEW, "Non-burst video mode with sync events\n"); |
| 282 | pkt_seq = pkt_seq_video_non_burst_sync_events; |
| 283 | } else { |
| 284 | printk(BIOS_SPEW, "Command mode\n"); |
| 285 | pkt_seq = pkt_seq_command_mode; |
| 286 | } |
| 287 | |
| 288 | err = tegra_dsi_get_muldiv(dsi->format, &mul, &div); |
| 289 | if (err < 0) |
| 290 | return err; |
| 291 | |
| 292 | err = tegra_dsi_get_format(dsi->format, &format); |
| 293 | if (err < 0) |
| 294 | return err; |
| 295 | |
| 296 | value = DSI_CONTROL_CHANNEL(0) | DSI_CONTROL_FORMAT(format) | |
| 297 | DSI_CONTROL_LANES(dsi->lanes - 1) | |
| 298 | DSI_CONTROL_SOURCE(pipe); |
| 299 | tegra_dsi_writel(dsi, value, DSI_CONTROL); |
| 300 | |
| 301 | tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD); |
| 302 | |
| 303 | value = DSI_HOST_CONTROL_HS; |
| 304 | tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); |
| 305 | |
| 306 | value = tegra_dsi_readl(dsi, DSI_CONTROL); |
| 307 | |
| 308 | if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) |
| 309 | value |= DSI_CONTROL_HS_CLK_CTRL; |
| 310 | |
| 311 | value &= ~DSI_CONTROL_TX_TRIG(3); |
| 312 | |
| 313 | /* enable DCS commands for command mode */ |
| 314 | if (dsi->flags & MIPI_DSI_MODE_VIDEO) |
| 315 | value &= ~DSI_CONTROL_DCS_ENABLE; |
| 316 | else |
| 317 | value |= DSI_CONTROL_DCS_ENABLE; |
| 318 | |
| 319 | value |= DSI_CONTROL_VIDEO_ENABLE; |
| 320 | value &= ~DSI_CONTROL_HOST_ENABLE; |
| 321 | tegra_dsi_writel(dsi, value, DSI_CONTROL); |
| 322 | |
| 323 | for (i = 0; i < NUM_PKT_SEQ; i++) |
| 324 | tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i); |
| 325 | |
| 326 | if (dsi->flags & MIPI_DSI_MODE_VIDEO) { |
| 327 | /* horizontal active pixels */ |
| 328 | hact = mode->xres * mul / div; |
| 329 | |
| 330 | /* horizontal sync width */ |
| 331 | hsw = (hsync_end(mode) - hsync_start(mode)) * mul / div; |
| 332 | |
| 333 | /* horizontal back porch */ |
| 334 | hbp = (htotal(mode) - hsync_end(mode)) * mul / div; |
| 335 | if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0) |
| 336 | hbp += hsw; |
| 337 | |
| 338 | /* horizontal front porch */ |
| 339 | hfp = (hsync_start(mode) - mode->xres) * mul / div; |
| 340 | |
| 341 | /* subtract packet overhead */ |
| 342 | hsw -= 10; |
| 343 | hbp -= 14; |
| 344 | hfp -= 8; |
| 345 | |
| 346 | tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1); |
| 347 | tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3); |
| 348 | tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5); |
| 349 | tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7); |
| 350 | |
| 351 | /* set SOL delay (for non-burst mode only) */ |
| 352 | tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY); |
| 353 | |
| 354 | /* TODO: implement ganged mode */ |
| 355 | } else { |
| 356 | u16 bytes; |
| 357 | if (dsi->ganged_mode) { |
| 358 | /* |
| 359 | * For ganged mode, assume symmetric left-right mode. |
| 360 | */ |
| 361 | bytes = 1 + (mode->xres / 2) * mul / div; |
| 362 | } else { |
| 363 | /* 1 byte (DCS command) + pixel data */ |
| 364 | bytes = 1 + mode->xres * mul / div; |
| 365 | } |
| 366 | |
| 367 | tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1); |
Jacob Garber | 9777048 | 2019-07-23 15:30:45 -0600 | [diff] [blame] | 368 | tegra_dsi_writel(dsi, (u32)bytes << 16, DSI_PKT_LEN_2_3); |
| 369 | tegra_dsi_writel(dsi, (u32)bytes << 16, DSI_PKT_LEN_4_5); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 370 | tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7); |
| 371 | |
| 372 | value = MIPI_DCS_WRITE_MEMORY_START << 8 | |
| 373 | MIPI_DCS_WRITE_MEMORY_CONTINUE; |
| 374 | tegra_dsi_writel(dsi, value, DSI_DCS_CMDS); |
| 375 | |
| 376 | /* set SOL delay */ |
| 377 | if (dsi->ganged_mode) { |
| 378 | unsigned long delay, bclk, bclk_ganged; |
| 379 | unsigned int lanes = dsi->ganged_lanes; |
| 380 | |
| 381 | /* SOL to valid, valid to FIFO and FIFO write delay */ |
| 382 | delay = 4 + 4 + 2; |
| 383 | delay = DIV_ROUND_UP(delay * mul, div * lanes); |
| 384 | /* FIFO read delay */ |
| 385 | delay = delay + 6; |
| 386 | |
| 387 | bclk = DIV_ROUND_UP(htotal(mode) * mul, div * lanes); |
| 388 | bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes); |
| 389 | value = bclk - bclk_ganged + delay + 20; |
| 390 | } else { |
| 391 | /* TODO: revisit for non-ganged mode */ |
| 392 | value = 8 * mul / div; |
| 393 | } |
| 394 | |
| 395 | tegra_dsi_writel(dsi, value, DSI_SOL_DELAY); |
| 396 | } |
| 397 | |
| 398 | if (dsi->slave) { |
| 399 | err = tegra_dsi_configure(dsi->slave, pipe, mode); |
| 400 | if (err < 0) |
| 401 | return err; |
| 402 | |
| 403 | /* |
| 404 | * enable ganged mode |
| 405 | */ |
| 406 | if (dsi->ganged_mode) { |
| 407 | tegra_dsi_ganged_enable(dsi, mode->xres / 2, |
| 408 | mode->xres / 2); |
| 409 | tegra_dsi_ganged_enable(dsi->slave, 0, mode->xres / 2); |
| 410 | } |
| 411 | } |
| 412 | return 0; |
| 413 | } |
| 414 | |
| 415 | static int tegra_output_dsi_enable(struct tegra_dsi *dsi, |
| 416 | const struct soc_nvidia_tegra210_config *config) |
| 417 | { |
| 418 | int err; |
| 419 | |
| 420 | if (dsi->enabled) |
| 421 | return 0; |
| 422 | |
| 423 | err = tegra_dsi_configure(dsi, 0, config); |
| 424 | if (err < 0) { |
| 425 | printk(BIOS_ERR, "DSI configuration failed\n"); |
| 426 | return err; |
| 427 | } |
| 428 | |
| 429 | /* enable DSI controller */ |
| 430 | tegra_dsi_enable(dsi); |
| 431 | |
| 432 | dsi->enabled = true; |
| 433 | return 0; |
| 434 | } |
| 435 | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 436 | static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk, |
| 437 | unsigned int vrefresh) |
| 438 | { |
| 439 | unsigned int timeout; |
| 440 | u32 value; |
| 441 | |
| 442 | /* one frame high-speed transmission timeout */ |
| 443 | timeout = (bclk / vrefresh) / 512; |
| 444 | value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout); |
| 445 | tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0); |
| 446 | |
| 447 | /* 2 ms peripheral timeout for panel */ |
| 448 | timeout = 2 * bclk / 512 * 1000; |
| 449 | value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000); |
| 450 | tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1); |
| 451 | |
| 452 | value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0); |
| 453 | tegra_dsi_writel(dsi, value, DSI_TO_TALLY); |
| 454 | |
| 455 | if (dsi->slave) |
| 456 | tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh); |
| 457 | } |
| 458 | |
| 459 | static int tegra_output_dsi_setup_clock(struct tegra_dsi *dsi, |
| 460 | const struct soc_nvidia_tegra210_config *config) |
| 461 | { |
| 462 | unsigned int mul, div, num_lanes; |
| 463 | unsigned long bclk; |
| 464 | unsigned long pclk = config->pixel_clock; |
| 465 | int plld; |
| 466 | int err; |
| 467 | struct display_controller *disp_ctrl = |
| 468 | (void *)config->display_controller; |
| 469 | unsigned int shift_clk_div; |
| 470 | |
| 471 | err = tegra_dsi_get_muldiv(dsi->format, &mul, &div); |
| 472 | if (err < 0) |
| 473 | return err; |
| 474 | |
| 475 | /* |
| 476 | * In ganged mode, account for the total number of lanes across both |
| 477 | * DSI channels so that the bit clock is properly computed. |
| 478 | */ |
| 479 | if (dsi->ganged_mode) |
| 480 | num_lanes = dsi->ganged_lanes; |
| 481 | else |
| 482 | num_lanes = dsi->lanes; |
| 483 | |
| 484 | /* compute byte clock */ |
| 485 | bclk = (pclk * mul) / (div * num_lanes); |
| 486 | |
| 487 | /* |
| 488 | * Compute bit clock and round up to the next MHz. |
| 489 | */ |
| 490 | plld = DIV_ROUND_UP(bclk * 8, USECS_PER_SEC) * USECS_PER_SEC; |
| 491 | |
| 492 | /* |
| 493 | * the actual rate on PLLD_OUT0 is 1/2 plld |
| 494 | */ |
| 495 | dsi->clk_rate = plld / 2; |
| 496 | if (dsi->slave) |
| 497 | dsi->slave->clk_rate = dsi->clk_rate; |
| 498 | |
| 499 | /* set up plld */ |
| 500 | plld = clock_configure_plld(plld); |
| 501 | if (plld == 0) { |
| 502 | printk(BIOS_ERR, "%s: clock init failed\n", __func__); |
| 503 | return -1; |
| 504 | } else |
| 505 | printk(BIOS_INFO, "%s: plld is configured to: %u\n", |
| 506 | __func__, plld); |
| 507 | |
| 508 | /* |
| 509 | * Derive pixel clock from bit clock using the shift clock divider. |
| 510 | * Note that this is only half of what we would expect, but we need |
| 511 | * that to make up for the fact that we divided the bit clock by a |
| 512 | * factor of two above. |
| 513 | */ |
| 514 | shift_clk_div = ((8 * mul) / (div * num_lanes)) - 2; |
| 515 | update_display_shift_clock_divider(disp_ctrl, shift_clk_div); |
| 516 | |
| 517 | tegra_dsi_set_timeout(dsi, bclk, config->refresh); |
| 518 | return plld/1000000; |
| 519 | } |
| 520 | |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 521 | static int tegra_dsi_pad_enable(struct tegra_dsi *dsi) |
| 522 | { |
| 523 | unsigned long value; |
| 524 | |
| 525 | value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0); |
| 526 | tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); |
| 527 | return 0; |
| 528 | } |
| 529 | |
| 530 | static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) |
| 531 | { |
| 532 | u32 value; |
| 533 | |
| 534 | tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0); |
| 535 | tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1); |
| 536 | tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2); |
| 537 | tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3); |
| 538 | tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4); |
| 539 | |
| 540 | /* start calibration */ |
| 541 | tegra_dsi_pad_enable(dsi); |
| 542 | |
| 543 | value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) | |
| 544 | DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) | |
| 545 | DSI_PAD_OUT_CLK(0x0); |
| 546 | tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2); |
| 547 | |
| 548 | value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | |
| 549 | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); |
| 550 | tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); |
| 551 | |
| 552 | return tegra_mipi_calibrate(dsi->mipi); |
| 553 | } |
| 554 | |
Elyes HAOUAS | 39303d5 | 2018-07-08 12:40:45 +0200 | [diff] [blame] | 555 | static const char *const error_report[16] = { |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 556 | "SoT Error", |
| 557 | "SoT Sync Error", |
| 558 | "EoT Sync Error", |
| 559 | "Escape Mode Entry Command Error", |
| 560 | "Low-Power Transmit Sync Error", |
| 561 | "Peripheral Timeout Error", |
| 562 | "False Control Error", |
| 563 | "Contention Detected", |
| 564 | "ECC Error, single-bit", |
| 565 | "ECC Error, multi-bit", |
| 566 | "Checksum Error", |
| 567 | "DSI Data Type Not Recognized", |
| 568 | "DSI VC ID Invalid", |
| 569 | "Invalid Transmission Length", |
| 570 | "Reserved", |
| 571 | "DSI Protocol Violation", |
| 572 | }; |
| 573 | |
| 574 | static int tegra_dsi_read_response(struct tegra_dsi *dsi, |
| 575 | const struct mipi_dsi_msg *msg, |
| 576 | unsigned int count) |
| 577 | { |
| 578 | u8 *rx = msg->rx_buf; |
| 579 | unsigned int i, j, k; |
| 580 | size_t size = 0; |
| 581 | u16 errors; |
| 582 | u32 value; |
| 583 | |
| 584 | /* read and parse packet header */ |
| 585 | value = tegra_dsi_readl(dsi, DSI_RD_DATA); |
| 586 | |
| 587 | switch (value & 0x3f) { |
| 588 | case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: |
| 589 | errors = (value >> 8) & 0xffff; |
| 590 | printk(BIOS_ERR, "Acknowledge and error report: %04x\n", |
| 591 | errors); |
| 592 | for (i = 0; i < ARRAY_SIZE(error_report); i++) |
| 593 | if (errors & BIT(i)) |
| 594 | printk(BIOS_INFO, " %2u: %s\n", i, |
| 595 | error_report[i]); |
| 596 | break; |
| 597 | |
| 598 | case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: |
| 599 | rx[0] = (value >> 8) & 0xff; |
| 600 | break; |
| 601 | |
| 602 | case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: |
| 603 | rx[0] = (value >> 8) & 0xff; |
| 604 | rx[1] = (value >> 16) & 0xff; |
| 605 | break; |
| 606 | |
| 607 | case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: |
| 608 | size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff); |
| 609 | break; |
| 610 | |
| 611 | case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: |
| 612 | size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff); |
| 613 | break; |
| 614 | |
| 615 | default: |
| 616 | printk(BIOS_ERR, "unhandled response type: %02x\n", |
| 617 | value & 0x3f); |
| 618 | break; |
| 619 | } |
| 620 | |
| 621 | size = MIN(size, msg->rx_len); |
| 622 | |
| 623 | if (msg->rx_buf && size > 0) { |
| 624 | for (i = 0, j = 0; i < count - 1; i++, j += 4) { |
| 625 | value = tegra_dsi_readl(dsi, DSI_RD_DATA); |
| 626 | |
| 627 | for (k = 0; k < 4 && (j + k) < msg->rx_len; k++) |
| 628 | rx[j + k] = (value >> (k << 3)) & 0xff; |
| 629 | } |
| 630 | } |
| 631 | return 0; |
| 632 | } |
| 633 | |
| 634 | static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout_ms) |
| 635 | { |
| 636 | u32 poll_interval_us = 2000; |
| 637 | u32 timeout_us = timeout_ms * 1000; |
| 638 | |
| 639 | tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER); |
| 640 | udelay(poll_interval_us); |
| 641 | |
| 642 | do { |
| 643 | u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER); |
| 644 | if ((value & DSI_TRIGGER_HOST) == 0) |
| 645 | return 0; |
| 646 | |
| 647 | //usleep_range(1000, 2000); |
| 648 | if (timeout_us > poll_interval_us) |
| 649 | timeout_us -= poll_interval_us; |
| 650 | else |
| 651 | break; |
| 652 | |
| 653 | udelay(poll_interval_us); |
| 654 | } while (1); |
| 655 | |
| 656 | printk(BIOS_ERR, "%s: ERROR: timeout waiting for transmission" |
| 657 | " to complete\n", __func__); |
| 658 | return -ETIMEDOUT; |
| 659 | } |
| 660 | |
| 661 | static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi, |
| 662 | unsigned long timeout_ms) |
| 663 | { |
| 664 | u32 poll_interval_us = 2000; |
| 665 | u32 timeout_us = timeout_ms * 1000; |
| 666 | |
| 667 | do { |
| 668 | u32 value = tegra_dsi_readl(dsi, DSI_STATUS); |
| 669 | u8 count = value & 0x1f; |
| 670 | |
| 671 | if (count > 0) |
| 672 | return count; |
| 673 | |
| 674 | if (timeout_us > poll_interval_us) |
| 675 | timeout_us -= poll_interval_us; |
| 676 | else |
| 677 | break; |
| 678 | |
| 679 | udelay(poll_interval_us); |
| 680 | } while (1); |
| 681 | |
| 682 | printk(BIOS_ERR, "%s: ERROR: timeout\n", __func__); |
| 683 | |
| 684 | return -ETIMEDOUT; |
| 685 | } |
| 686 | |
| 687 | static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host, |
| 688 | const struct mipi_dsi_msg *msg) |
| 689 | { |
| 690 | struct tegra_dsi *dsi = host_to_tegra(host); |
| 691 | const u8 *tx = msg->tx_buf; |
| 692 | unsigned int count, i, j; |
| 693 | u32 value; |
| 694 | int err; |
| 695 | |
| 696 | if (msg->tx_len > dsi->video_fifo_depth * 4) |
| 697 | return -ENOSPC; |
| 698 | |
| 699 | /* reset underflow/overflow flags */ |
| 700 | value = tegra_dsi_readl(dsi, DSI_STATUS); |
| 701 | if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) { |
| 702 | value = DSI_HOST_CONTROL_FIFO_RESET; |
| 703 | tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); |
| 704 | udelay(20); // usleep_range(10, 20); |
| 705 | } |
| 706 | |
| 707 | value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); |
| 708 | value |= DSI_POWER_CONTROL_ENABLE; |
| 709 | tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); |
| 710 | |
| 711 | udelay(7000); //usleep_range(5000, 10000); |
| 712 | |
| 713 | value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | |
| 714 | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC; |
| 715 | |
| 716 | if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0) |
| 717 | value |= DSI_HOST_CONTROL_HS; |
| 718 | |
| 719 | /* |
| 720 | * The host FIFO has a maximum of 64 words, so larger transmissions |
| 721 | * need to use the video FIFO. |
| 722 | */ |
| 723 | if (msg->tx_len > dsi->host_fifo_depth * 4) |
| 724 | value |= DSI_HOST_CONTROL_FIFO_SEL; |
| 725 | |
| 726 | tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); |
| 727 | |
| 728 | /* |
| 729 | * For reads and messages with explicitly requested ACK, generate a |
| 730 | * BTA sequence after the transmission of the packet. |
| 731 | */ |
| 732 | if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) || |
| 733 | (msg->rx_buf && msg->rx_len > 0)) { |
| 734 | value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL); |
| 735 | value |= DSI_HOST_CONTROL_PKT_BTA; |
| 736 | tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); |
| 737 | } |
| 738 | |
| 739 | value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE; |
| 740 | tegra_dsi_writel(dsi, value, DSI_CONTROL); |
| 741 | |
| 742 | /* write packet header */ |
| 743 | value = ((msg->channel & 0x3) << 6) | (msg->type & 0x3f); |
| 744 | |
| 745 | if (tx && msg->tx_len > 0) |
| 746 | value |= tx[0] << 8; |
| 747 | |
| 748 | if (tx && msg->tx_len > 1) |
| 749 | value |= tx[1] << 16; |
| 750 | |
| 751 | tegra_dsi_writel(dsi, value, DSI_WR_DATA); |
| 752 | |
| 753 | /* write payload (if any) */ |
Jacob Garber | bd00fb1 | 2019-07-23 15:45:20 -0600 | [diff] [blame] | 754 | if (tx && msg->tx_len > 2) { |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 755 | for (j = 2; j < msg->tx_len; j += 4) { |
| 756 | value = 0; |
| 757 | |
| 758 | for (i = 0; i < 4 && j + i < msg->tx_len; i++) |
| 759 | value |= tx[j + i] << (i << 3); |
| 760 | |
| 761 | tegra_dsi_writel(dsi, value, DSI_WR_DATA); |
| 762 | } |
| 763 | } |
| 764 | |
| 765 | err = tegra_dsi_transmit(dsi, 250); |
| 766 | if (err < 0) { |
| 767 | printk(BIOS_INFO, "Failed to transmit. %d\n", err); |
| 768 | return err; |
| 769 | } |
| 770 | |
| 771 | if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) || |
| 772 | (msg->rx_buf && msg->rx_len > 0)) { |
| 773 | err = tegra_dsi_wait_for_response(dsi, 250); |
| 774 | if (err < 0) { |
| 775 | printk(BIOS_INFO, "Failed to read response. %d\n", err); |
| 776 | return err; |
| 777 | } |
| 778 | count = err; |
| 779 | |
| 780 | value = tegra_dsi_readl(dsi, DSI_RD_DATA); |
| 781 | switch (value) { |
| 782 | case 0x84: |
| 783 | printk(BIOS_INFO, "ACK\n"); |
| 784 | break; |
| 785 | |
| 786 | case 0x87: |
| 787 | printk(BIOS_INFO, "ESCAPE\n"); |
| 788 | break; |
| 789 | |
| 790 | default: |
| 791 | printk(BIOS_INFO, "unknown status: %08x\n", value); |
| 792 | break; |
| 793 | } |
| 794 | |
| 795 | if (count > 1) { |
| 796 | err = tegra_dsi_read_response(dsi, msg, count); |
| 797 | if (err < 0) |
| 798 | printk(BIOS_INFO, |
| 799 | "failed to parse response: %d\n", |
| 800 | err); |
| 801 | else { |
| 802 | /* |
| 803 | * For read commands, return the number of |
| 804 | * bytes returned by the peripheral. |
| 805 | */ |
| 806 | count = err; |
| 807 | } |
| 808 | } |
| 809 | } else { |
| 810 | /* |
| 811 | * For write commands, we have transmitted the 4-byte header |
| 812 | * plus the variable-length payload. |
| 813 | */ |
| 814 | count = 4 + msg->tx_len; |
| 815 | } |
| 816 | |
| 817 | return count; |
| 818 | } |
| 819 | |
| 820 | static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi, |
| 821 | struct tegra_dsi *slave) |
| 822 | { |
| 823 | /* |
| 824 | * The number of ganged lanes is the sum of lanes of all peripherals |
| 825 | * in the gang. |
| 826 | */ |
| 827 | dsi->slave->ganged_lanes = dsi->lanes + dsi->slave->lanes; |
| 828 | dsi->slave->ganged_mode = 1; |
| 829 | |
| 830 | dsi->ganged_lanes = dsi->lanes + dsi->slave->lanes; |
| 831 | dsi->ganged_mode = 1; |
| 832 | return 0; |
| 833 | } |
| 834 | |
| 835 | static int tegra_dsi_host_attach(struct mipi_dsi_host *host, |
| 836 | struct mipi_dsi_device *device) |
| 837 | { |
| 838 | struct tegra_dsi *dsi = host_to_tegra(host); |
| 839 | int err; |
| 840 | |
| 841 | dsi->flags = device->mode_flags; |
| 842 | dsi->format = device->format; |
| 843 | dsi->lanes = device->lanes; |
| 844 | |
| 845 | if (dsi->master) { |
| 846 | err = tegra_dsi_ganged_setup(dsi->master, dsi); |
| 847 | if (err < 0) { |
| 848 | printk(BIOS_ERR, "failed to set up ganged mode: %d\n", |
| 849 | err); |
| 850 | return err; |
| 851 | } |
| 852 | } |
| 853 | return 0; |
| 854 | } |
| 855 | |
| 856 | static const struct mipi_dsi_host_ops tegra_dsi_host_ops = { |
| 857 | .attach = tegra_dsi_host_attach, |
| 858 | .transfer = tegra_dsi_host_transfer, |
| 859 | }; |
| 860 | |
| 861 | static int dsi_probe_if(int dsi_index, |
| 862 | struct soc_nvidia_tegra210_config *config) |
| 863 | { |
| 864 | struct tegra_dsi *dsi = &dsi_data[dsi_index]; |
| 865 | int err; |
| 866 | |
| 867 | tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_CONTROL); |
| 868 | |
| 869 | /* |
| 870 | * Set default value. Will be taken from attached device once detected |
| 871 | */ |
Elyes HAOUAS | 88607a4 | 2018-10-05 10:36:45 +0200 | [diff] [blame] | 872 | dsi->flags = 0; |
| 873 | dsi->format = MIPI_DSI_FMT_RGB888; |
| 874 | dsi->lanes = 4; |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 875 | |
| 876 | /* get tegra_mipi_device */ |
Elyes HAOUAS | 88607a4 | 2018-10-05 10:36:45 +0200 | [diff] [blame] | 877 | dsi->mipi = tegra_mipi_request(&mipi_device_data[dsi_index], dsi_index); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 878 | |
| 879 | /* calibrate */ |
| 880 | err = tegra_dsi_pad_calibrate(dsi); |
| 881 | if (err < 0) { |
| 882 | printk(BIOS_ERR, "MIPI calibration failed: %d\n", err); |
| 883 | return err; |
| 884 | } |
| 885 | |
| 886 | dsi->host.ops = &tegra_dsi_host_ops; |
| 887 | err = mipi_dsi_host_register(&dsi->host); |
| 888 | if (err < 0) { |
| 889 | printk(BIOS_ERR, "failed to register DSI host: %d\n", err); |
| 890 | return err; |
| 891 | } |
| 892 | |
| 893 | /* get panel */ |
| 894 | dsi->panel = panel_jdi_dsi_probe((struct mipi_dsi_device *)dsi->host.dev); |
| 895 | if (IS_ERR_PTR(dsi->panel)) { |
| 896 | printk(BIOS_ERR, "failed to get dsi panel\n"); |
| 897 | return -EPTR; |
| 898 | } |
| 899 | dsi->panel->mode = config; |
| 900 | return 0; |
| 901 | } |
| 902 | |
| 903 | static int dsi_probe(struct soc_nvidia_tegra210_config *config) |
| 904 | { |
| 905 | dsi_probe_if(DSI_A, config); |
| 906 | dsi_probe_if(DSI_B, config); |
| 907 | return 0; |
| 908 | } |
| 909 | |
| 910 | static void tegra_dsi_init_regs(struct tegra_dsi *dsi) |
| 911 | { |
| 912 | int i; |
| 913 | for (i = 0; i < ARRAY_SIZE(init_reg); i++) |
| 914 | tegra_dsi_writel(dsi, 0, init_reg[i]); |
| 915 | |
| 916 | if (dsi->slave) |
| 917 | tegra_dsi_init_regs(dsi->slave); |
| 918 | } |
| 919 | |
| 920 | static int dsi_enable(struct soc_nvidia_tegra210_config *config) |
| 921 | { |
| 922 | struct tegra_dsi *dsi_a = &dsi_data[DSI_A]; |
| 923 | |
| 924 | dsi_probe(config); |
| 925 | |
| 926 | /* set up clock and TimeOutRegisters */ |
| 927 | tegra_output_dsi_setup_clock(dsi_a, config); |
| 928 | |
| 929 | /* configure APB_MISC_GP_MIPI_PAD_CTRL_0 */ |
| 930 | write32((unsigned int *)APB_MISC_GP_MIPI_PAD_CTRL_0, DSIB_MODE_DSI); |
| 931 | |
| 932 | /* configure phy interface timing registers */ |
| 933 | tegra_dsi_set_phy_timing(dsi_a); |
| 934 | |
| 935 | /* Initialize DSI registers */ |
| 936 | tegra_dsi_init_regs(dsi_a); |
| 937 | |
| 938 | /* prepare panel */ |
| 939 | panel_jdi_prepare(dsi_a->panel); |
| 940 | |
| 941 | /* enable dsi */ |
| 942 | if (tegra_output_dsi_enable(dsi_a, config)) { |
| 943 | printk(BIOS_ERR,"%s: Error: failed to enable dsi output.\n", |
| 944 | __func__); |
| 945 | return -1; |
| 946 | } |
| 947 | |
| 948 | return 0; |
| 949 | } |
| 950 | |
Elyes HAOUAS | 3fcb218 | 2018-05-25 10:03:57 +0200 | [diff] [blame] | 951 | void dsi_display_startup(struct device *dev) |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 952 | { |
| 953 | struct soc_nvidia_tegra210_config *config = dev->chip_info; |
| 954 | struct display_controller *disp_ctrl = |
| 955 | (void *)config->display_controller; |
| 956 | u32 plld_rate; |
| 957 | |
| 958 | u32 framebuffer_size_mb = config->framebuffer_size / MiB; |
| 959 | u32 framebuffer_base_mb= config->framebuffer_base / MiB; |
| 960 | |
| 961 | printk(BIOS_INFO, "%s: entry: disp_ctrl: %p.\n", |
| 962 | __func__, disp_ctrl); |
| 963 | |
| 964 | if (disp_ctrl == NULL) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 965 | printk(BIOS_ERR, "No dc is assigned by dt.\n"); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 966 | return; |
| 967 | } |
| 968 | |
| 969 | if (framebuffer_size_mb == 0){ |
| 970 | framebuffer_size_mb = ALIGN_UP(config->display_xres * |
| 971 | config->display_yres * |
| 972 | (config->framebuffer_bits_per_pixel / 8), MiB)/MiB; |
| 973 | } |
| 974 | |
| 975 | config->framebuffer_size = framebuffer_size_mb * MiB; |
| 976 | config->framebuffer_base = framebuffer_base_mb * MiB; |
| 977 | |
| 978 | /* |
| 979 | * The plld is programmed with the assumption of the SHIFT_CLK_DIVIDER |
| 980 | * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the |
| 981 | * update_display_mode() for detail. |
| 982 | */ |
| 983 | /* set default plld */ |
| 984 | plld_rate = clock_configure_plld(config->pixel_clock * 2); |
| 985 | if (plld_rate == 0) { |
| 986 | printk(BIOS_ERR, "dc: clock init failed\n"); |
| 987 | return; |
| 988 | } |
| 989 | |
| 990 | /* set disp1's clock source to PLLD_OUT0 */ |
| 991 | clock_configure_source(disp1, PLLD_OUT0, (plld_rate/KHz)); |
| 992 | |
| 993 | /* Init dc */ |
| 994 | if (tegra_dc_init(disp_ctrl)) { |
| 995 | printk(BIOS_ERR, "dc: init failed\n"); |
| 996 | return; |
| 997 | } |
| 998 | |
| 999 | /* Configure dc mode */ |
| 1000 | if (update_display_mode(disp_ctrl, config)) { |
| 1001 | printk(BIOS_ERR, "dc: failed to configure display mode.\n"); |
| 1002 | return; |
| 1003 | } |
| 1004 | |
| 1005 | /* Configure and enable dsi controller and panel */ |
| 1006 | if (dsi_enable(config)) { |
| 1007 | printk(BIOS_ERR, "%s: failed to enable dsi controllers.\n", |
| 1008 | __func__); |
| 1009 | return; |
| 1010 | } |
| 1011 | |
| 1012 | /* Set up window */ |
| 1013 | update_window(config); |
| 1014 | printk(BIOS_INFO, "%s: display init done.\n", __func__); |
| 1015 | |
| 1016 | /* Save panel information to cb tables */ |
| 1017 | pass_mode_info_to_payload(config); |
| 1018 | |
| 1019 | /* |
| 1020 | * After this point, it is payload's responsibility to allocate |
| 1021 | * framebuffer and sets the base address to dc's |
| 1022 | * WINBUF_START_ADDR register and enables window by setting dc's |
| 1023 | * DISP_DISP_WIN_OPTIONS register. |
| 1024 | */ |
| 1025 | } |