Angel Pons | 6ad9176 | 2020-04-03 01:23:24 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Mario Scheithauer | 5716b4c | 2018-11-14 13:27:05 +0100 | [diff] [blame] | 2 | |
| 3 | #include <bootstate.h> |
| 4 | #include <console/console.h> |
Mario Scheithauer | a94a153 | 2018-11-28 09:13:28 +0100 | [diff] [blame] | 5 | #include <device/pci_def.h> |
Mario Scheithauer | 5716b4c | 2018-11-14 13:27:05 +0100 | [diff] [blame] | 6 | #include <device/pci_ids.h> |
| 7 | #include <device/pci_ops.h> |
| 8 | #include <gpio.h> |
| 9 | #include <hwilib.h> |
| 10 | #include <intelblocks/lpc_lib.h> |
| 11 | #include <intelblocks/pcr.h> |
| 12 | #include <soc/pcr_ids.h> |
Mario Scheithauer | 5716b4c | 2018-11-14 13:27:05 +0100 | [diff] [blame] | 13 | #include <baseboard/variants.h> |
Elyes HAOUAS | e39db68 | 2019-05-15 21:12:31 +0200 | [diff] [blame] | 14 | #include <types.h> |
Mario Scheithauer | 5716b4c | 2018-11-14 13:27:05 +0100 | [diff] [blame] | 15 | |
| 16 | #define TX_DWORD3 0xa8c |
| 17 | |
| 18 | void variant_mainboard_final(void) |
| 19 | { |
Mario Scheithauer | 5716b4c | 2018-11-14 13:27:05 +0100 | [diff] [blame] | 20 | struct device *dev = NULL; |
| 21 | |
| 22 | /* |
Mario Scheithauer | 5716b4c | 2018-11-14 13:27:05 +0100 | [diff] [blame] | 23 | * PIR6 register mapping for PCIe root ports |
| 24 | * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA# |
| 25 | */ |
| 26 | pcr_write16(PID_ITSS, 0x314c, 0x0321); |
| 27 | |
Mario Scheithauer | 5716b4c | 2018-11-14 13:27:05 +0100 | [diff] [blame] | 28 | /* Enable CLKRUN_EN for power gating LPC */ |
| 29 | lpc_enable_pci_clk_cntl(); |
| 30 | |
| 31 | /* |
| 32 | * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2 |
| 33 | * offset 0x341D bit3 and bit0. |
| 34 | * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2 |
| 35 | * offset 0x341C bit [3:0]. |
| 36 | */ |
| 37 | pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN)); |
| 38 | |
| 39 | /* |
| 40 | * Correct the SATA transmit signal via the High Speed I/O Transmit |
| 41 | * Control Register 3. |
| 42 | * Bit [23:16] set the output voltage swing for TX line. |
| 43 | * The value 0x4a sets the swing level to 0.58 V. |
| 44 | */ |
| 45 | pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16)); |
Mario Scheithauer | a94a153 | 2018-11-28 09:13:28 +0100 | [diff] [blame] | 46 | |
| 47 | /* Set Master Enable for on-board PCI device. */ |
| 48 | dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0); |
| 49 | if (dev) { |
Angel Pons | 28ed787 | 2020-11-10 20:07:33 +0100 | [diff] [blame] | 50 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); |
Mario Scheithauer | 1a5ce95 | 2018-11-28 09:21:58 +0100 | [diff] [blame] | 51 | |
| 52 | /* Disable clock outputs 0-3 (CLKOUT) for upstream XIO2001 PCIe |
| 53 | * to PCI Bridge. */ |
| 54 | struct device *parent = dev->bus->dev; |
| 55 | if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001) |
| 56 | pci_write_config8(parent, 0xd8, 0x0f); |
| 57 | } |
| 58 | |
| 59 | /* Disable clock outputs 1-5 (CLKOUT) for another XIO2001 PCIe to PCI |
| 60 | * Bridge on this mainboard. |
| 61 | */ |
| 62 | dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403f, 0); |
| 63 | if (dev) { |
| 64 | struct device *parent = dev->bus->dev; |
| 65 | if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001) |
| 66 | pci_write_config8(parent, 0xd8, 0x3e); |
Mario Scheithauer | a94a153 | 2018-11-28 09:13:28 +0100 | [diff] [blame] | 67 | } |
Mario Scheithauer | 5716b4c | 2018-11-14 13:27:05 +0100 | [diff] [blame] | 68 | } |
| 69 | |
Mario Scheithauer | 5716b4c | 2018-11-14 13:27:05 +0100 | [diff] [blame] | 70 | static void finalize_boot(void *unused) |
| 71 | { |
| 72 | /* Set coreboot ready LED. */ |
| 73 | gpio_output(CNV_RGI_DT, 1); |
| 74 | } |
| 75 | |
Mario Scheithauer | 5716b4c | 2018-11-14 13:27:05 +0100 | [diff] [blame] | 76 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); |