Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 3 | #include <console/console.h> |
| 4 | #include <cpu/intel/smm_reloc.h> |
| 5 | #include <cpu/intel/turbo.h> |
Michael Niewöhner | 10ae1cf | 2020-10-11 14:05:32 +0200 | [diff] [blame] | 6 | #include <cpu/intel/common/common.h> |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 7 | #include <cpu/x86/lapic.h> |
| 8 | #include <cpu/x86/mp.h> |
| 9 | #include <cpu/x86/msr.h> |
| 10 | #include <device/pci.h> |
| 11 | #include <fsp/api.h> |
| 12 | #include <intelblocks/cpulib.h> |
| 13 | #include <intelblocks/mp_init.h> |
| 14 | #include <intelblocks/msr.h> |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 15 | #include <soc/cpu.h> |
| 16 | #include <soc/msr.h> |
| 17 | #include <soc/pci_devs.h> |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 18 | #include <soc/soc_chip.h> |
| 19 | |
| 20 | static void soc_fsp_load(void) |
| 21 | { |
Kyösti Mälkki | cc93c6e | 2021-01-09 22:53:52 +0200 | [diff] [blame] | 22 | fsps_load(); |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 23 | } |
| 24 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 25 | static void configure_misc(void) |
| 26 | { |
| 27 | msr_t msr; |
| 28 | |
| 29 | config_t *conf = config_of_soc(); |
| 30 | |
| 31 | msr = rdmsr(IA32_MISC_ENABLE); |
| 32 | msr.lo |= (1 << 0); /* Fast String enable */ |
| 33 | msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ |
| 34 | wrmsr(IA32_MISC_ENABLE, msr); |
| 35 | |
| 36 | /* Set EIST status */ |
| 37 | cpu_set_eist(conf->eist_enable); |
| 38 | |
| 39 | /* Disable Thermal interrupts */ |
| 40 | msr.lo = 0; |
| 41 | msr.hi = 0; |
| 42 | wrmsr(IA32_THERM_INTERRUPT, msr); |
| 43 | |
| 44 | /* Enable package critical interrupt only */ |
| 45 | msr.lo = 1 << 4; |
| 46 | msr.hi = 0; |
| 47 | wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); |
| 48 | |
| 49 | /* Enable PROCHOT */ |
| 50 | msr = rdmsr(MSR_POWER_CTL); |
| 51 | msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/ |
| 52 | msr.lo |= (1 << 23); /* Lock it */ |
| 53 | wrmsr(MSR_POWER_CTL, msr); |
| 54 | } |
| 55 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 56 | /* All CPUs including BSP will run the following function. */ |
| 57 | void soc_core_init(struct device *cpu) |
| 58 | { |
| 59 | /* Clear out pending MCEs */ |
| 60 | /* TODO(adurbin): This should only be done on a cold boot. Also, some |
| 61 | * of these banks are core vs package scope. For now every CPU clears |
| 62 | * every bank. */ |
| 63 | mca_configure(); |
| 64 | |
| 65 | /* Enable the local CPU apics */ |
| 66 | enable_lapic_tpr(); |
| 67 | setup_lapic(); |
| 68 | |
| 69 | /* Configure Enhanced SpeedStep and Thermal Sensors */ |
| 70 | configure_misc(); |
| 71 | |
Tan, Lean Sheng | 05dfe31 | 2020-08-25 20:40:17 -0700 | [diff] [blame] | 72 | enable_pm_timer_emulation(); |
| 73 | |
| 74 | /* Enable Direct Cache Access */ |
| 75 | configure_dca_cap(); |
| 76 | |
| 77 | /* Set energy policy */ |
| 78 | set_energy_perf_bias(ENERGY_POLICY_NORMAL); |
| 79 | |
| 80 | /* Enable Turbo */ |
| 81 | enable_turbo(); |
| 82 | } |
| 83 | |
| 84 | static void per_cpu_smm_trigger(void) |
| 85 | { |
| 86 | /* Relocate the SMM handler. */ |
| 87 | smm_relocate(); |
| 88 | } |
| 89 | |
| 90 | static void post_mp_init(void) |
| 91 | { |
| 92 | /* Set Max Ratio */ |
| 93 | cpu_set_max_ratio(); |
| 94 | |
| 95 | /* |
| 96 | * Now that all APs have been relocated as well as the BSP let SMIs |
| 97 | * start flowing. |
| 98 | */ |
| 99 | global_smi_enable(); |
| 100 | } |
| 101 | |
| 102 | static const struct mp_ops mp_ops = { |
| 103 | /* |
| 104 | * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, |
| 105 | * that are set prior to ramstage. |
| 106 | * Real MTRRs programming are being done after resource allocation. |
| 107 | */ |
| 108 | .pre_mp_init = soc_fsp_load, |
| 109 | .get_cpu_count = get_cpu_count, |
| 110 | .get_smm_info = smm_info, |
| 111 | .get_microcode_info = get_microcode_info, |
| 112 | .pre_mp_smm_init = smm_initialize, |
| 113 | .per_cpu_smm_trigger = per_cpu_smm_trigger, |
| 114 | .relocation_handler = smm_relocation_handler, |
| 115 | .post_mp_init = post_mp_init, |
| 116 | }; |
| 117 | |
| 118 | void soc_init_cpus(struct bus *cpu_bus) |
| 119 | { |
| 120 | if (mp_init_with_smm(cpu_bus, &mp_ops)) |
| 121 | printk(BIOS_ERR, "MP initialization failure.\n"); |
| 122 | |
| 123 | /* Thermal throttle activation offset */ |
| 124 | configure_tcc_thermal_target(); |
| 125 | } |